5M240ZT100I5N vs 5M240ZT100C5N 비교
다음의 상세 나란히 비교: 5M240ZT100I5N 제조: Altera 및 5M240ZT100C5N 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | 5M240ZT100I5N | 5M240ZT100C5N |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | 활성 | 활성 |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $4.81 | $4.98 |
| Family | MAX V | MAX V |
| Series | 5M240Z | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Elements | 240 | — |
| Macrocells | 192 | 192 |
| User Flash Memory | 8 Kbit | 8 Kbits |
| Maximum User I/O | 114 | — |
| User I/O Pins (per datasheet) | 79 | — |
| 핀 수 | 100 | — |
| Package Type | TQFP-100 (T100) | — |
| Package Body Size | 14 x 14 mm | — |
| Lead Pitch | 0.50 mm | — |
| Core Voltage (VCCINT) | 1.8 V | — |
| I/O Bank Voltage (VCCIO) | 1.2 V to 3.3 V (bank-dependent) | — |
| Speed Grade | -5 | — |
| Maximum Internal Frequency | 118.3 MHz | 118.3 MHz |
| Pin-to-Pin Delay (tPD1) | 7.5 ns (per datasheet header) | — |
| 동작 온도 | -40 C to +100 C (Industrial) | 0C to +85C (commercial grade) |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | JTAG (IEEE 1149.1) |
| Configuration Memory | Non-volatile flash (instant-on) | Internal flash (non-volatile, instant-on) |
| 실장 유형 | Surface Mount | Surface Mount |
| Lead-Free / RoHS | Yes (LEAD FREE per datasheet header) | — |
| MSL 레벨 | [DATA_NEEDED: MSL Level] | [DATA_NEEDED: MSL level] |
| AEC-Q100 Automotive | Not qualified (Industrial grade) | — |
| Logic Elements (LEs) | — | 240 |
| User I/Os | — | 79 |
| Pin-to-Pin Logic Delay (Tpd1) | — | 7.5 ns (per distributor classification) |
| Operating Voltage (VCCINT) | — | 3.3 V (internal 1.8 V core derived) |
| I/O Bank Voltages Supported | — | 1.5 V, 1.8 V, 2.5 V, 3.3 V LVCMOS/LVTTL |
| 패키지 | — | TQFP-100 (14 x 14 mm, 0.5 mm pitch) |
| RoHS 상태 | — | Compliant (per LCSC listing) |