A42MX16-PQG100A vs A42MX16-PQ100IX39 Vergleich
Detaillierter Direktvergleich von A42MX16-PQG100A von Microchip Technology und A42MX16-PQ100IX39 von Microchip Technology. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Microchip Technology
A42MX16-PQG100A - 24K Gate 5V FPGA 100-BQFP | Microchip
A42MX16-PQG100A ✓ AktivMicrochip Technology
A42MX16-PQ100IX39 - 24K Gate MX FPGA | Microchip | 100-Pin PQFP
A42MX16-PQ100IX39 ✓ AktivSpezifikationsvergleich
| Parameter | A42MX16-PQG100A | A42MX16-PQ100IX39 |
|---|---|---|
| Marke | Microchip Technology | Microchip Technology |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,00 | $31,90 |
| Family | MX (42MX) FPGA | MX (40MX and 42MX) |
| System Gates | 24000 | — |
| Logic Cells | 608 | 1232 |
| User I/O | 83 | — |
| Versorgungsspannung | 5.0 V | 5.0 V |
| Maximum Frequency | 153 MHz | — |
| Process Technology | 0.45 um CMOS | — |
| Programming Technology | Antifuse (one-time programmable) | — |
| Gehäuse | 100-BQFP (PQFP) | 100-pin PQFP |
| Montageart | Surface Mount | — |
| Grade | Automotive (A suffix) | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | — |
| Packaging | Tray | — |
| Configuration | Self-contained (no external config memory) | Antifuse (non-volatile) |
| Design Security | High (OTP antifuse, no bitstream exposure) | — |
| RoHS-Status | Lead free (per distributor listing) | Compliant |
| Design Software | Microchip Libero SoC | — |
| Equivalent System Gates | — | 24000 |
| Configurable Logic Blocks (CLBs) | — | 608 |
| User I/O Pins | — | 83 |
| Maximale Taktfrequenz | — | 56 MHz |
| Betriebstemperaturbereich | — | -40°C to +85°C (industrial) |
| Terminal Pitch | — | 0.635 mm |
| PCI Compliance | — | PCI Local Bus Specification version 2.1 |
| On-Chip Operation | — | 200 MHz |
| Clock-to-Output | — | 6.1 ns |
| JTAG Boundary Scan | — | IEEE Standard 1149.1 |