ADS62P28IRGC25 vs ADS62P48IRGC25 Vergleich
Detaillierter Direktvergleich von ADS62P28IRGC25 von Texas Instruments und ADS62P48IRGC25 von Texas Instruments. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Texas Instruments
ADS62P28IRGC25 - Dual 12-Bit 210-MSPS ADC with DDR LVDS/CMOS | TI
ADS62P28IRGC25 ✓ AktivTexas Instruments
ADS62P48IRGC25 - Dual 14-Bit 210MSPS ADC | Texas Instruments
ADS62P48IRGC25 ✓ AktivSpezifikationsvergleich
| Parameter | ADS62P28IRGC25 | ADS62P48IRGC25 |
|---|---|---|
| Marke | Texas Instruments | Texas Instruments |
| Kategorie | ADC/DAC | ADC/DAC |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $17,50 | $49,20 |
| Auflösung | 12 bit | 14 bit |
| Number of Channels | 2 (dual) | 2 (Dual) |
| Abtastrate | 210 MSPS | — |
| Architecture | Pipelined | Pipelined |
| Input Type | Differential / Single-ended | Differential analog inputs |
| Full-Scale Input Range | 1 Vpp to 2 Vpp (programmable) | — |
| Output Interface | DDR LVDS / Parallel CMOS (selectable) | DDR LVDS / Parallel CMOS (selectable) |
| SNR | 70 dBFS (typical at 70 MHz IF) | — |
| SFDR | 85 dBc (typical at 70 MHz IF) | — |
| Analog Supply Voltage | 3.3 V | 1.8 V |
| Digital Supply Voltage | 1.8 V (LVDS mode) | 3.3 V |
| Power Dissipation | 1.7 W typical | — |
| Input Bandwidth | 450 MHz (3 dB) | — |
| Gehäuse | 64-VQFN (RGC) 9x9 mm with exposed pad | — |
| Betriebstemperatur | -40 C to +85 C (Industrial) | — |
| RoHS-Status | Compliant | Compliant |
| Sample Rate (max) | — | 210 MSPS |
| Betriebstemperaturbereich | — | -40 C to +85 C (Industrial) |
| Gehäuse / Bauform | — | 64-VQFN (RGC) 9x9 mm (HVQCCN) |
| Pin-Anzahl | — | 64 |
| Montageart | — | Surface Mount |
| MSL-Level | — | 3 |
| Lead Free | — | Yes |
| Input Clock Type | — | LVDS differential clock |
| Internal Dither | — | Yes (programmable) |
| Programmable Gain | — | Yes (improves SFDR at lower FS inputs) |