ADS62P28IRGC25 vs ADS62P48IRGC25 Comparación
Comparación detallada lado a lado de ADS62P28IRGC25 por Texas Instruments y ADS62P48IRGC25 por Texas Instruments. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Texas Instruments
ADS62P28IRGC25 - Dual 12-Bit 210-MSPS ADC with DDR LVDS/CMOS | TI
ADS62P28IRGC25 ✓ ActivoTexas Instruments
ADS62P48IRGC25 - Dual 14-Bit 210MSPS ADC | Texas Instruments
ADS62P48IRGC25 ✓ ActivoComparación de especificaciones
| Parámetro | ADS62P28IRGC25 | ADS62P48IRGC25 |
|---|---|---|
| Marca | Texas Instruments | Texas Instruments |
| Categoría | ADC/DAC | ADC/DAC |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $17,50 | $49,20 |
| Resolución | 12 bit | 14 bit |
| Number of Channels | 2 (dual) | 2 (Dual) |
| Frecuencia de muestreo | 210 MSPS | — |
| Architecture | Pipelined | Pipelined |
| Input Type | Differential / Single-ended | Differential analog inputs |
| Full-Scale Input Range | 1 Vpp to 2 Vpp (programmable) | — |
| Output Interface | DDR LVDS / Parallel CMOS (selectable) | DDR LVDS / Parallel CMOS (selectable) |
| SNR | 70 dBFS (typical at 70 MHz IF) | — |
| SFDR | 85 dBc (typical at 70 MHz IF) | — |
| Analog Supply Voltage | 3.3 V | 1.8 V |
| Digital Supply Voltage | 1.8 V (LVDS mode) | 3.3 V |
| Power Dissipation | 1.7 W typical | — |
| Input Bandwidth | 450 MHz (3 dB) | — |
| Encapsulado | 64-VQFN (RGC) 9x9 mm with exposed pad | — |
| Temperatura de funcionamiento | -40 C to +85 C (Industrial) | — |
| Estado RoHS | Compliant | Compliant |
| Sample Rate (max) | — | 210 MSPS |
| Rango de temperatura de funcionamiento | — | -40 C to +85 C (Industrial) |
| Encapsulado / Carcasa | — | 64-VQFN (RGC) 9x9 mm (HVQCCN) |
| Recuento de pines | — | 64 |
| Tipo de montaje | — | Surface Mount |
| Nivel MSL | — | 3 |
| Lead Free | — | Yes |
| Input Clock Type | — | LVDS differential clock |
| Internal Dither | — | Yes (programmable) |
| Programmable Gain | — | Yes (improves SFDR at lower FS inputs) |