ATF16V8B-10SI vs ATF16V8B-15PU Vergleich

Detaillierter Direktvergleich von ATF16V8B-10SI von Microchip Technology und ATF16V8B-15PU von Microchip Technology. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Microchip Technology
ATF16V8B-10SI ATF16V8B-10SI - 10ns 250-Gate Erasable PLD | Microchip

ATF16V8B-10SI - 10ns 250-Gate Erasable PLD | Microchip

ATF16V8B-10SI ✓ Aktiv
Microchip Technology
ATF16V8B-15PU ATF16V8B-15PU - 15 ns 8-Macrocell 5V PLD | Microchip

ATF16V8B-15PU - 15 ns 8-Macrocell 5V PLD | Microchip

ATF16V8B-15PU ✓ Aktiv

Spezifikationsvergleich

Parameter ATF16V8B-10SI ATF16V8B-15PU
Marke Microchip Technology Microchip Technology
Kategorie Logic ICs Logic ICs
Lebenszyklusstatus Aktiv Aktiv
Device Type Electrically Erasable Programmable Logic Device (PLD) 16V8 electrically erasable programmable logic device
Logic Density 250 gates —
Macrocell Count 8 macrocells —
Maximum Inputs Up to 16 inputs Up to 16 inputs
I/O Count 8 I/Os —
Output Count 8 outputs —
Product Terms per Output 8 product terms 8 product terms
Propagation Delay 10 ns —
Versorgungsspannung 5 V —
Power Class Standard power Standard power
Gehäuse 20-SOIC, 7.50 mm width 20-pin PDIP
Temperature Grade Industrial temperature —
Programming Technology Electrically erasable —
Operating Modes 3 automatically selected modes —
Architecture Compatibility Generic 16R8 and most 20-pin combinatorial PLDs —
Fusemap Compatibility JEDEC fusemap compatible —
Montageart Surface mount —
RoHS-Status [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
REACH Status [DATA_NEEDED: REACH compliance status] [DATA_NEEDED: REACH status]
Architecture — PAL-compatible 20-pin architecture
Macrocells — 8 macrocells
Gate Equivalent Capacity — 250 gates
Propagation Delay Grade — 15 ns
Nominal Supply Voltage — 5 V
User I/O — 8 I/Os
Registered Outputs — 8 outputs
Configuration Technology — Electrically erasable Flash memory
Logic Family — CMOS
Package Suffix — P
Green Package — Green
Programming — Electrically erasable PLD programming
AEC-Q100 Qualification — [DATA_NEEDED: AEC-Q100 qualification]
Betriebstemperaturbereich — [DATA_NEEDED: operating temperature range]

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