ATSAMA5D21C-CU vs ATSAMA5D27C-CU Vergleich
Detaillierter Direktvergleich von ATSAMA5D21C-CU von Microchip Technology und ATSAMA5D27C-CU von Microchip Technology. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Microchip Technology
ATSAMA5D21C-CU - 500MHz Cortex-A5 MPU | Microchip 196-TFBGA
ATSAMA5D21C-CU ✓ AktivMicrochip Technology
ATSAMA5D27C-CU - ARM Cortex-A5 MPU 500MHz 289-LFBGA | Microchip
ATSAMA5D27C-CU ✓ AktivSpezifikationsvergleich
| Parameter | ATSAMA5D21C-CU | ATSAMA5D27C-CU |
|---|---|---|
| Marke | Microchip Technology | Microchip Technology |
| Kategorie | Microcontrollers | Microcontrollers |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,85 | $11,90 |
| Manufacturer | Microchip Technology | — |
| Series | SAMA5D2 | — |
| Core Processor | ARM Cortex-A5 | — |
| Number of Cores | 1 | — |
| Bit Width | 32-bit | — |
| Maximum CPU Clock | 500 MHz | — |
| L1 Instruction Cache | 32 KB | — |
| L1 Data Cache | 32 KB | — |
| L2 Cache | 128 KB | — |
| Gehäuse | 196-TFBGA 11x11 mm, 0.8 mm pitch | 289-LFBGA (14x14 mm, 0.8 mm pitch) |
| Integrated DRAM | Up to 1 Gbit DDR2 or 2 Gbit LPDDR2 SDRAM (SiP) | — |
| External Memory Bus | DDR2/DDR3L/LPDDR2/LPDDR3, QSPI, eMMC, SD/MMC | — |
| Ethernet | 10/100/1000 Mbps with IEEE 1588 PTP | — |
| USB | USB HS Host + Device, USB FS Host + Device | — |
| CAN | 2x CAN-FD | — |
| Other Connectivity | 2x SD/SDIO/MMC, I2C, SPI, UART, I2S | — |
| ADC | 12-bit ADC | — |
| Graphics | LCD controller (up to 1024x768) | — |
| Crypto Accelerators | AES, SHA, TRNG, secure boot, tamper detection | — |
| Audio | Class D amplifier, I2S, S/PDIF | — |
| Backup Mode Current | 5 uA | 5 uA typical |
| Betriebstemperaturbereich | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Grade | Industrial (green, MRLC) | — |
| Montageart | Surface Mount (TFBGA) | Surface Mount |
| MSL-Level | 3 | — |
| RoHS-Status | Compliant | Compliant |
| Core Architecture | — | ARM Cortex-A5 |
| Core Count | — | 1 |
| Datenbusbreite | — | 32-bit |
| Maximale Taktfrequenz | — | 500 MHz |
| On-chip SRAM | — | 128 KB |
| Instruction Cache | — | 32 KB |
| Data Cache | — | 32 KB |
| External Memory Support | — | DDR2, DDR3L, LPDDR2, LPDDR3 (16-bit interface) |
| Floating Point Unit | — | Yes (VFPv4) |
| Versorgungsspannung | — | [DATA_NEEDED: core/IO supply voltage] |