ATSAMA5D42A-CUR vs ATSAMA5D42A-CU Vergleich
Detaillierter Direktvergleich von ATSAMA5D42A-CUR von Microchip Technology und ATSAMA5D42A-CU von Microchip Technology. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Microchip Technology
ATSAMA5D42A-CUR - 600MHz ARM Cortex-A5 MPU, 361-TFBGA | Microchip
ATSAMA5D42A-CUR ✓ AktivMicrochip Technology
ATSAMA5D42A-CU - ARM Cortex-A5 MPU 600MHz 361-TFBGA | Microchip
ATSAMA5D42A-CU ✓ AktivSpezifikationsvergleich
| Parameter | ATSAMA5D42A-CUR | ATSAMA5D42A-CU |
|---|---|---|
| Marke | Microchip Technology | Microchip Technology |
| Kategorie | Microcontrollers | Microcontrollers |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $18,40 | $18,24 |
| Core Architecture | ARM Cortex-A5 (32-bit, single core) | ARMv7-A with Thumb-2, NEON, FPU, MMU |
| Maximum CPU Clock | 600 MHz | — |
| SIMD Engine | ARM NEON | — |
| Floating Point Unit | Yes (single and double precision) | — |
| L1 Cache | 32 KB I-cache + 32 KB D-cache (per core) | — |
| L2 Cache | 128 KB | 128 KByte |
| Internal ROM | 128 KB | — |
| Internal SRAM | 128 KB | 128 KByte |
| External Memory Support | LPDDR, LPDDR2, DDR2 | — |
| Gehäuse | 361-TFBGA (16 x 16 mm) | 361-TFBGA (16x16 mm, 0.8 mm pitch) |
| ADC | 5-channel, 10-bit with resistive touchscreen controller | — |
| Crypto Acceleration | AES, SHA-256, TRNG (hardware) | — |
| Memory Integrity Monitor | ICM based on SHA-256 (secure boot) | — |
| USB | USB 2.0 High-Speed Host and Device | — |
| Networking | 10/100 Mbps EMAC with MII/RMII | — |
| Betriebstemperatur | -40 C to +85 C (industrial) | -40C to +85C (industrial) |
| Supply Voltage (Core) | [DATA_NEEDED: VDDCORE nominal] | — |
| Montageart | Surface Mount (BGA) | Surface Mount (BGA) |
| Core Processor | — | ARM Cortex-A5 |
| Number of Cores | — | 1 |
| Datenbusbreite | — | 32-bit |
| Maximum Clock Speed | — | 600 MHz |
| L1 Instruction Cache | — | 32 KByte |
| L1 Data Cache | — | 32 KByte |
| Operating Voltage (Core) | — | 1.2 V to 1.32 V |
| Operating Voltage (I/O) | — | 1.8 V / 3.3 V |
| DDR Memory Controller | — | DDR2/LPDDR/DDR3, 16-bit data bus |
| MSL-Level | — | 3 (per JEDEC J-STD-020) |
| RoHS-Status | — | Compliant |