EP1810GI-45 vs EP1810JC-45 Vergleich
Detaillierter Direktvergleich von EP1810GI-45 von Altera und EP1810JC-45 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP1810GI-45 | EP1810JC-45 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $56,40 | $21,10 |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | — |
| Family | Altera Classic EPLD | EP1810 (Classic EPLD Family) |
| Macrocells | 24 | 48 |
| Flip-Flops | 48 | — |
| Propagation Delay (tpd) | 45 ns | 45 ns |
| Speed Grade | -45 | — |
| Technology | CMOS | CMOS, UV-erasable |
| Package Type | Ceramic Pin Grid Array with UV window | — |
| Pin-Anzahl | 68 | 68 |
| Montageart | Through-Hole | Surface Mount |
| Programmable | Yes (UV-erasable, electrically programmable) | — |
| RoHS-Status | Non-compliant (ceramic PGA) | [DATA_NEEDED: RoHS compliance not stated in verified data] |
| Lead-Free | No | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | — |
| Versorgungsspannung | [DATA_NEEDED: VCC range] | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Equivalent Gates | — | 2100 gates |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 48 |
| Total User I/O | — | 60 |
| Maximale Taktfrequenz | — | 33.3 MHz |
| Maximum Supply Voltage | — | 5.25 V |
| Gehäuse | — | PLCC-68 (QCCJ, J-Lead, windowed ceramic) |
| Package Code | — | QCCJ |
| Temperature Grade | — | Commercial |