EP1810GI-45 vs EP1810JI-35 Vergleich
Detaillierter Direktvergleich von EP1810GI-45 von Altera und EP1810JI-35 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP1810GI-45 | EP1810JI-35 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $56,40 | $18,60 |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | — |
| Family | Altera Classic EPLD | — |
| Macrocells | 24 | 48 |
| Flip-Flops | 48 | — |
| Propagation Delay (tpd) | 45 ns | — |
| Speed Grade | -45 | -35 |
| Technology | CMOS | — |
| Package Type | Ceramic Pin Grid Array with UV window | — |
| Pin-Anzahl | 68 | — |
| Montageart | Through-Hole | Through-Hole (J-lead) |
| Programmable | Yes (UV-erasable, electrically programmable) | — |
| RoHS-Status | Non-compliant (ceramic PGA) | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] |
| Lead-Free | No | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | -40C to +85C (Industrial) |
| Versorgungsspannung | [DATA_NEEDED: VCC range] | 5 V (typical classic EPLD) |
| Device Family | — | Classic EPLD |
| Logic Array Blocks | — | 8 LABs of 16 macrocells |
| Dedicated Inputs | — | 48 |
| Pin-to-Pin Propagation Delay (tPD) | — | 35 ns |
| Gehäuse | — | 28-pin JLCC (J-leaded ceramic, windowed) |
| Process Technology | — | CMOS EPROM (UV-erasable) |
| Programmability | — | UV-erase, windowed for lab reprogram |
| MSL-Level | — | [DATA_NEEDED: MSL rating] |
| Programming Interface | — | JEDEC fuse file via legacy programmer |