EP1810GI-45 vs EP1810JI-35 Comparación
Comparación detallada lado a lado de EP1810GI-45 por Altera y EP1810JI-35 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1810GI-45 | EP1810JI-35 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $56,40 | $18,60 |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | — |
| Family | Altera Classic EPLD | — |
| Macrocells | 24 | 48 |
| Flip-Flops | 48 | — |
| Propagation Delay (tpd) | 45 ns | — |
| Speed Grade | -45 | -35 |
| Technology | CMOS | — |
| Package Type | Ceramic Pin Grid Array with UV window | — |
| Recuento de pines | 68 | — |
| Tipo de montaje | Through-Hole | Through-Hole (J-lead) |
| Programmable | Yes (UV-erasable, electrically programmable) | — |
| Estado RoHS | Non-compliant (ceramic PGA) | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] |
| Lead-Free | No | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | -40C to +85C (Industrial) |
| Tensión de alimentación | [DATA_NEEDED: VCC range] | 5 V (typical classic EPLD) |
| Device Family | — | Classic EPLD |
| Logic Array Blocks | — | 8 LABs of 16 macrocells |
| Dedicated Inputs | — | 48 |
| Pin-to-Pin Propagation Delay (tPD) | — | 35 ns |
| Encapsulado | — | 28-pin JLCC (J-leaded ceramic, windowed) |
| Process Technology | — | CMOS EPROM (UV-erasable) |
| Programmability | — | UV-erase, windowed for lab reprogram |
| Nivel MSL | — | [DATA_NEEDED: MSL rating] |
| Programming Interface | — | JEDEC fuse file via legacy programmer |