EP1810GM883 vs EP1810GC-35 Vergleich
Detaillierter Direktvergleich von EP1810GM883 von Altera und EP1810GC-35 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EP1810GC-35 - UV PLD, 40ns, CMOS, CPGA68 | Altera / Rochester
EP1810GC-35 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EP1810GM883 | EP1810GC-35 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $175,00 | $177,12 |
| Family | Classic EPLD (EP1810 series) | — |
| Device Type | UV-Erasable Programmable Logic Device (EPLD) | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 48 | 16 |
| Dedicated Inputs | 12 | — |
| User I/O Pins | 48 | — |
| Total Terminals | 68 | — |
| Global Clocks | 4 | — |
| Supply Voltage (Vcc) | 4.5 V to 5.5 V (nominal 5 V) | — |
| Propagation Delay (tpd) | 45 ns (max) | — |
| Maximum Toggle Frequency (fmax) | [DATA_NEEDED: fmax value not in source data; Classic EPLD family typical 35-80 MHz depending on grade] | — |
| Process Technology | CMOS, UV-erasable | — |
| Gehäuse | 68-Pin Ceramic Pin Grid Array (PGA) | CPGA-68 (Ceramic Pin Grid Array, 68-pin) |
| Betriebstemperatur | -55C to +125C (MIL-STD-883 Class B) | [DATA_NEEDED: operating temperature range] |
| Screening | MIL-STD-883 Class B (suffix '883' denotes MIL processing) | — |
| Montageart | Through-Hole (PGA socket) | Through Hole |
| RoHS-Status | [DATA_NEEDED: hermetic ceramic PGA is typically non-RoHS due to lead-bearing solder/finish; not confirmed in source data] | Not applicable (legacy ceramic package) |
| Lead-Free | [DATA_NEEDED: military 883B screened parts commonly use SnPb finish] | — |
| Logic Family | — | Altera Classic EPLD |
| Technology | — | CMOS, UV-erasable EPROM cells |
| Anzahl der Pins | — | 68 |
| Propagation Delay (tpd max) | — | 40 ns |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| I/O Standard | — | TTL-compatible |
| Programming Method | — | UV erasure + EPROM programming |
| Versorgungsspannung | — | [DATA_NEEDED: VCC range] |
| Lead-Free Status | — | Not applicable |
| Manufacturer (current source) | — | Rochester Electronics (authorized Altera EPLD partner) |
| Original Manufacturer | — | Altera Corporation (now Intel FPGA) |