EP1810GM883 vs EP1810GC-35 Comparaison
Comparaison détaillée côte à côte de EP1810GM883 par Altera et EP1810GC-35 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP1810GM883 | EP1810GC-35 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $175,00 | $177,12 |
| Family | Classic EPLD (EP1810 series) | — |
| Device Type | UV-Erasable Programmable Logic Device (EPLD) | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 48 | 16 |
| Dedicated Inputs | 12 | — |
| User I/O Pins | 48 | — |
| Total Terminals | 68 | — |
| Global Clocks | 4 | — |
| Supply Voltage (Vcc) | 4.5 V to 5.5 V (nominal 5 V) | — |
| Propagation Delay (tpd) | 45 ns (max) | — |
| Maximum Toggle Frequency (fmax) | [DATA_NEEDED: fmax value not in source data; Classic EPLD family typical 35-80 MHz depending on grade] | — |
| Process Technology | CMOS, UV-erasable | — |
| Boîtier | 68-Pin Ceramic Pin Grid Array (PGA) | CPGA-68 (Ceramic Pin Grid Array, 68-pin) |
| Température de fonctionnement | -55C to +125C (MIL-STD-883 Class B) | [DATA_NEEDED: operating temperature range] |
| Screening | MIL-STD-883 Class B (suffix '883' denotes MIL processing) | — |
| Type de montage | Through-Hole (PGA socket) | Through Hole |
| Statut RoHS | [DATA_NEEDED: hermetic ceramic PGA is typically non-RoHS due to lead-bearing solder/finish; not confirmed in source data] | Not applicable (legacy ceramic package) |
| Lead-Free | [DATA_NEEDED: military 883B screened parts commonly use SnPb finish] | — |
| Logic Family | — | Altera Classic EPLD |
| Technology | — | CMOS, UV-erasable EPROM cells |
| Nombre de broches | — | 68 |
| Propagation Delay (tpd max) | — | 40 ns |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| I/O Standard | — | TTL-compatible |
| Programming Method | — | UV erasure + EPROM programming |
| Tension d'alimentation | — | [DATA_NEEDED: VCC range] |
| Lead-Free Status | — | Not applicable |
| Manufacturer (current source) | — | Rochester Electronics (authorized Altera EPLD partner) |
| Original Manufacturer | — | Altera Corporation (now Intel FPGA) |