EP1810JC-25 vs EP1810GM883 Vergleich

Detaillierter Direktvergleich von EP1810JC-25 von Intel und EP1810GM883 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP1810JC-25 EP1810GM883
Marke Intel Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus NRND Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $6,80 $175,00
Product Type Classic EPLD (Erasable Programmable Logic Device) —
Family Altera/Intel Classic EPLD (EP1810 series) Classic EPLD (EP1810 series)
Macrocells 48 48
Propagation Delay (tPD) 25 ns —
Maximum Toggle Frequency [DATA_NEEDED: max fMAX] —
Input Lines 60 (including I/O) —
I/O Lines 48 —
Dedicated Inputs 12 12
External Clock Inputs 4 —
Supply Voltage (VCC) 4.75 V to 5.25 V —
Betriebstemperatur -40 °C to 85 °C (industrial, per distributor listings) -55C to +125C (MIL-STD-883 Class B)
Technology CMOS, UV-erasable (windowed ceramic DIP) —
Gehäuse 28-pin ceramic DIP (J) with quartz window 68-Pin Ceramic Pin Grid Array (PGA)
Montageart Through-hole Through-Hole (PGA socket)
Erasure Method UV light (windowed package) —
RoHS-Status [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: hermetic ceramic PGA is typically non-RoHS due to lead-bearing solder/finish; not confirmed in source data]
Lebenszyklusstatus NRND (Not Recommended for New Designs) —
Device Type — UV-Erasable Programmable Logic Device (EPLD)
User I/O Pins — 48
Total Terminals — 68
Global Clocks — 4
Supply Voltage (Vcc) — 4.5 V to 5.5 V (nominal 5 V)
Propagation Delay (tpd) — 45 ns (max)
Maximum Toggle Frequency (fmax) — [DATA_NEEDED: fmax value not in source data; Classic EPLD family typical 35-80 MHz depending on grade]
Process Technology — CMOS, UV-erasable
Screening — MIL-STD-883 Class B (suffix '883' denotes MIL processing)
Lead-Free — [DATA_NEEDED: military 883B screened parts commonly use SnPb finish]

Datenblätter & Ressourcen

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