EP1810JC-25 vs EP1810GM883 Comparaison
Comparaison détaillée côte à côte de EP1810JC-25 par Intel et EP1810GM883 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP1810JC-25 | EP1810GM883 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $6,80 | $175,00 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera/Intel Classic EPLD (EP1810 series) | Classic EPLD (EP1810 series) |
| Macrocells | 48 | 48 |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Toggle Frequency | [DATA_NEEDED: max fMAX] | — |
| Input Lines | 60 (including I/O) | — |
| I/O Lines | 48 | — |
| Dedicated Inputs | 12 | 12 |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Température de fonctionnement | -40 °C to 85 °C (industrial, per distributor listings) | -55C to +125C (MIL-STD-883 Class B) |
| Technology | CMOS, UV-erasable (windowed ceramic DIP) | — |
| Boîtier | 28-pin ceramic DIP (J) with quartz window | 68-Pin Ceramic Pin Grid Array (PGA) |
| Type de montage | Through-hole | Through-Hole (PGA socket) |
| Erasure Method | UV light (windowed package) | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: hermetic ceramic PGA is typically non-RoHS due to lead-bearing solder/finish; not confirmed in source data] |
| Statut du cycle de vie | NRND (Not Recommended for New Designs) | — |
| Device Type | — | UV-Erasable Programmable Logic Device (EPLD) |
| User I/O Pins | — | 48 |
| Total Terminals | — | 68 |
| Global Clocks | — | 4 |
| Supply Voltage (Vcc) | — | 4.5 V to 5.5 V (nominal 5 V) |
| Propagation Delay (tpd) | — | 45 ns (max) |
| Maximum Toggle Frequency (fmax) | — | [DATA_NEEDED: fmax value not in source data; Classic EPLD family typical 35-80 MHz depending on grade] |
| Process Technology | — | CMOS, UV-erasable |
| Screening | — | MIL-STD-883 Class B (suffix '883' denotes MIL processing) |
| Lead-Free | — | [DATA_NEEDED: military 883B screened parts commonly use SnPb finish] |