EP1810JC-25 vs EP1810JC35 Vergleich

Detaillierter Direktvergleich von EP1810JC-25 von Intel und EP1810JC35 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP1810JC-25 EP1810JC35
Marke Intel Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus NRND Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $6,80 $9,75
Product Type Classic EPLD (Erasable Programmable Logic Device) UV-erasable / OTP Complex PLD (EPLD)
Family Altera/Intel Classic EPLD (EP1810 series) Altera Classic EPLD
Macrocells 48 48
Propagation Delay (tPD) 25 ns 35 ns
Maximum Toggle Frequency [DATA_NEEDED: max fMAX] —
Input Lines 60 (including I/O) —
I/O Lines 48 —
Dedicated Inputs 12 —
External Clock Inputs 4 —
Supply Voltage (VCC) 4.75 V to 5.25 V —
Betriebstemperatur -40 °C to 85 °C (industrial, per distributor listings) 0 C to +70 C (Commercial)
Technology CMOS, UV-erasable (windowed ceramic DIP) —
Gehäuse 28-pin ceramic DIP (J) with quartz window PLCC-68 (J-lead, ceramic)
Montageart Through-hole —
Erasure Method UV light (windowed package) —
RoHS-Status [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS compliance for EP1810JC35]
Lebenszyklusstatus NRND (Not Recommended for New Designs) —
Logic Gates (typ.) — [DATA_NEEDED: logic gates count]
Maximum User I/O Pins — [DATA_NEEDED: user I/O count for PLCC-68]
Maximale Taktfrequenz — 40 MHz
Supply Voltage (VCC max) — 5.25 V
Supply Voltage (VCC min) — [DATA_NEEDED: VCC minimum]
Process Technology — CMOS EPROM cell
Package Code — QCCJ
Terminal Form — J-BEND
Number of Terminals — 68
Programming — UV-erase (windowed) or OTP
Development Tool — Altera MAX+plus II / A+plus

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