EP1810JC-45 vs EP1810GC-35AB Vergleich
Detaillierter Direktvergleich von EP1810JC-45 von Altera und EP1810GC-35AB von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP1810JC-45 | EP1810GC-35AB |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $21,10 | $9,95 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | EP1810 (Classic EPLD Family) | — |
| Macrocells | 48 | — |
| Equivalent Gates | 2100 gates | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 48 | — |
| Total User I/O | 60 | — |
| Propagation Delay (tpd) | 45 ns | — |
| Maximale Taktfrequenz | 33.3 MHz | — |
| Technology | CMOS, UV-erasable | CMOS EPROM |
| Maximum Supply Voltage | 5.25 V | — |
| Gehäuse | PLCC-68 (QCCJ, J-Lead, windowed ceramic) | — |
| Pin-Anzahl | 68 | — |
| Package Code | QCCJ | — |
| Temperature Grade | Commercial | — |
| Montageart | Surface Mount | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance not stated in verified data] | unknown |
| Product Family | — | Classic EPLD |
| Number of Macrocells | — | 48 |
| Number of Usable Gates | — | 1200 |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| Number of I/O Pins | — | 48 |
| Dedicated Input Pins | — | 12 |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Toggle Frequency | — | 62.5 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Package Type | — | Pin Grid Array (PGA), ceramic |
| Betriebstemperatur | — | [DATA_NEEDED: operating temperature range] |
| Programming Method | — | UV-erasable EPROM, in-system via JTAG-like interface |