EP1810JC-45 vs EP1810GC-35AB Comparación
Comparación detallada lado a lado de EP1810JC-45 por Altera y EP1810GC-35AB por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1810JC-45 | EP1810GC-35AB |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $21,10 | $9,95 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | EP1810 (Classic EPLD Family) | — |
| Macrocells | 48 | — |
| Equivalent Gates | 2100 gates | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 48 | — |
| Total User I/O | 60 | — |
| Propagation Delay (tpd) | 45 ns | — |
| Frecuencia de reloj máxima | 33.3 MHz | — |
| Technology | CMOS, UV-erasable | CMOS EPROM |
| Maximum Supply Voltage | 5.25 V | — |
| Encapsulado | PLCC-68 (QCCJ, J-Lead, windowed ceramic) | — |
| Recuento de pines | 68 | — |
| Package Code | QCCJ | — |
| Temperature Grade | Commercial | — |
| Tipo de montaje | Surface Mount | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance not stated in verified data] | unknown |
| Product Family | — | Classic EPLD |
| Number of Macrocells | — | 48 |
| Number of Usable Gates | — | 1200 |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| Number of I/O Pins | — | 48 |
| Dedicated Input Pins | — | 12 |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Toggle Frequency | — | 62.5 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Package Type | — | Pin Grid Array (PGA), ceramic |
| Temperatura de funcionamiento | — | [DATA_NEEDED: operating temperature range] |
| Programming Method | — | UV-erasable EPROM, in-system via JTAG-like interface |