EP1810JC35 vs EP1810GC-35 Vergleich
Detaillierter Direktvergleich von EP1810JC35 von Altera und EP1810GC-35 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EP1810GC-35 - UV PLD, 40ns, CMOS, CPGA68 | Altera / Rochester
EP1810GC-35 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EP1810JC35 | EP1810GC-35 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,75 | $177,12 |
| Family | Altera Classic EPLD | — |
| Product Type | UV-erasable / OTP Complex PLD (EPLD) | — |
| Macrocells | 48 | 16 |
| Logic Gates (typ.) | [DATA_NEEDED: logic gates count] | — |
| Maximum User I/O Pins | [DATA_NEEDED: user I/O count for PLCC-68] | — |
| Propagation Delay (tPD) | 35 ns | — |
| Maximale Taktfrequenz | 40 MHz | — |
| Supply Voltage (VCC max) | 5.25 V | — |
| Supply Voltage (VCC min) | [DATA_NEEDED: VCC minimum] | — |
| Process Technology | CMOS EPROM cell | — |
| Betriebstemperatur | 0 C to +70 C (Commercial) | [DATA_NEEDED: operating temperature range] |
| Gehäuse | PLCC-68 (J-lead, ceramic) | CPGA-68 (Ceramic Pin Grid Array, 68-pin) |
| Package Code | QCCJ | — |
| Terminal Form | J-BEND | — |
| Number of Terminals | 68 | — |
| Programming | UV-erase (windowed) or OTP | — |
| Development Tool | Altera MAX+plus II / A+plus | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance for EP1810JC35] | Not applicable (legacy ceramic package) |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Family | — | Altera Classic EPLD |
| Technology | — | CMOS, UV-erasable EPROM cells |
| Anzahl der Pins | — | 68 |
| Propagation Delay (tpd max) | — | 40 ns |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| I/O Standard | — | TTL-compatible |
| Programming Method | — | UV erasure + EPROM programming |
| Versorgungsspannung | — | [DATA_NEEDED: VCC range] |
| Montageart | — | Through Hole |
| Lead-Free Status | — | Not applicable |
| Manufacturer (current source) | — | Rochester Electronics (authorized Altera EPLD partner) |
| Original Manufacturer | — | Altera Corporation (now Intel FPGA) |