EP1810JC35 vs EP1810GC-35 비교
다음의 상세 나란히 비교: EP1810JC35 제조: Altera 및 EP1810GC-35 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP1810JC35 | EP1810GC-35 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | 최종 구매 |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $9.75 | $177.12 |
| Family | Altera Classic EPLD | — |
| Product Type | UV-erasable / OTP Complex PLD (EPLD) | — |
| Macrocells | 48 | 16 |
| Logic Gates (typ.) | [DATA_NEEDED: logic gates count] | — |
| Maximum User I/O Pins | [DATA_NEEDED: user I/O count for PLCC-68] | — |
| Propagation Delay (tPD) | 35 ns | — |
| 최대 클록 주파수 | 40 MHz | — |
| Supply Voltage (VCC max) | 5.25 V | — |
| Supply Voltage (VCC min) | [DATA_NEEDED: VCC minimum] | — |
| Process Technology | CMOS EPROM cell | — |
| 동작 온도 | 0 C to +70 C (Commercial) | [DATA_NEEDED: operating temperature range] |
| 패키지 | PLCC-68 (J-lead, ceramic) | CPGA-68 (Ceramic Pin Grid Array, 68-pin) |
| Package Code | QCCJ | — |
| Terminal Form | J-BEND | — |
| Number of Terminals | 68 | — |
| Programming | UV-erase (windowed) or OTP | — |
| Development Tool | Altera MAX+plus II / A+plus | — |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance for EP1810JC35] | Not applicable (legacy ceramic package) |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Family | — | Altera Classic EPLD |
| Technology | — | CMOS, UV-erasable EPROM cells |
| 핀 수 | — | 68 |
| Propagation Delay (tpd max) | — | 40 ns |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| I/O Standard | — | TTL-compatible |
| Programming Method | — | UV erasure + EPROM programming |
| 공급 전압 | — | [DATA_NEEDED: VCC range] |
| 실장 유형 | — | Through Hole |
| Lead-Free Status | — | Not applicable |
| Manufacturer (current source) | — | Rochester Electronics (authorized Altera EPLD partner) |
| Original Manufacturer | — | Altera Corporation (now Intel FPGA) |