EP1810JI-35 vs EP1810GI-45 Vergleich
Detaillierter Direktvergleich von EP1810JI-35 von Intel und EP1810GI-45 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP1810JI-35 | EP1810GI-45 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $18,60 | $56,40 |
| Device Family | Classic EPLD | — |
| Macrocells | 48 | 24 |
| Logic Array Blocks | 8 LABs of 16 macrocells | — |
| Dedicated Inputs | 48 | — |
| Pin-to-Pin Propagation Delay (tPD) | 35 ns | — |
| Speed Grade | -35 | -45 |
| Gehäuse | 28-pin JLCC (J-leaded ceramic, windowed) | — |
| Process Technology | CMOS EPROM (UV-erasable) | — |
| Betriebstemperatur | -40C to +85C (Industrial) | [DATA_NEEDED: operating temperature range] |
| Versorgungsspannung | 5 V (typical classic EPLD) | [DATA_NEEDED: VCC range] |
| Programmability | UV-erase, windowed for lab reprogram | — |
| Montageart | Through-Hole (J-lead) | Through-Hole |
| RoHS-Status | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] | Non-compliant (ceramic PGA) |
| MSL-Level | [DATA_NEEDED: MSL rating] | — |
| Programming Interface | JEDEC fuse file via legacy programmer | — |
| Device Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Family | — | Altera Classic EPLD |
| Flip-Flops | — | 48 |
| Propagation Delay (tpd) | — | 45 ns |
| Technology | — | CMOS |
| Package Type | — | Ceramic Pin Grid Array with UV window |
| Pin-Anzahl | — | 68 |
| Programmable | — | Yes (UV-erasable, electrically programmable) |
| Lead-Free | — | No |