EP1810JI-35 vs EP1810LI-45 Vergleich

Detaillierter Direktvergleich von EP1810JI-35 von Intel und EP1810LI-45 von Rochester Electronics. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP1810JI-35 EP1810LI-45
Marke Intel Rochester Electronics
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Aktiv
Lagerstatus In Stock In Stock
Stückpreis (USD) $18,60 $64,10
Device Family Classic EPLD —
Macrocells 48 48
Logic Array Blocks 8 LABs of 16 macrocells —
Dedicated Inputs 48 —
Pin-to-Pin Propagation Delay (tPD) 35 ns —
Speed Grade -35 —
Gehäuse 28-pin JLCC (J-leaded ceramic, windowed) 68-pin PLCC / PQCC68 (J-Lead)
Process Technology CMOS EPROM (UV-erasable) —
Betriebstemperatur -40C to +85C (Industrial) —
Versorgungsspannung 5 V (typical classic EPLD) 5 V
Programmability UV-erase, windowed for lab reprogram —
Montageart Through-Hole (J-lead) —
RoHS-Status [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] [DATA_NEEDED: RoHS status]
MSL-Level [DATA_NEEDED: MSL rating] —
Programming Interface JEDEC fuse file via legacy programmer —
Product Type — EPLD (Erasable Programmable Logic Device)
Family — Altera Classic
Usable Gates — 900
Maximum User I/O — 64 inputs / 48 outputs
Pin-to-Pin Logic Delay (tPD) — 45 ns
Counter Frequency (fCNT) — up to 100 MHz
Setup Time (tSU) — [DATA_NEEDED: setup time]
Technology — CMOS, UV-erasable EPROM configuration
Betriebstemperaturbereich — -40 C to +85 C (Industrial, 'I' suffix)
Logic Blocks — 12 LABs of 4 macrocells each
Configuration Memory — Non-volatile UV-erasable EPROM
Programming Method — Altera programming hardware with MAX+PLUS II / legacy tools
Manufacturer — Rochester Electronics (licensed continuation of Altera / Intel PSG Classic EPLD line)

Datenblätter & Ressourcen

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