EP1810JI-35 vs EP1810LI-45 Comparação
Comparação detalhada lado a lado de EP1810JI-35 por Intel e EP1810LI-45 por Rochester Electronics. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Rochester Electronics
EP1810LI-45 - Classic EPLD, 900 Gates, 48 Macrocells, 45ns, PQCC68 | Rochester Electronics (Altera)
EP1810LI-45 ✓ AtivoComparação de especificações
| Parâmetro | EP1810JI-35 | EP1810LI-45 |
|---|---|---|
| Marca | Intel | Rochester Electronics |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Ativo |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $18,60 | $64,10 |
| Device Family | Classic EPLD | — |
| Macrocells | 48 | 48 |
| Logic Array Blocks | 8 LABs of 16 macrocells | — |
| Dedicated Inputs | 48 | — |
| Pin-to-Pin Propagation Delay (tPD) | 35 ns | — |
| Speed Grade | -35 | — |
| Encapsulamento | 28-pin JLCC (J-leaded ceramic, windowed) | 68-pin PLCC / PQCC68 (J-Lead) |
| Process Technology | CMOS EPROM (UV-erasable) | — |
| Temperatura de operação | -40C to +85C (Industrial) | — |
| Tensão de alimentação | 5 V (typical classic EPLD) | 5 V |
| Programmability | UV-erase, windowed for lab reprogram | — |
| Tipo de montagem | Through-Hole (J-lead) | — |
| Status RoHS | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] | [DATA_NEEDED: RoHS status] |
| Nível MSL | [DATA_NEEDED: MSL rating] | — |
| Programming Interface | JEDEC fuse file via legacy programmer | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Family | — | Altera Classic |
| Usable Gates | — | 900 |
| Maximum User I/O | — | 64 inputs / 48 outputs |
| Pin-to-Pin Logic Delay (tPD) | — | 45 ns |
| Counter Frequency (fCNT) | — | up to 100 MHz |
| Setup Time (tSU) | — | [DATA_NEEDED: setup time] |
| Technology | — | CMOS, UV-erasable EPROM configuration |
| Faixa de temperatura de operação | — | -40 C to +85 C (Industrial, 'I' suffix) |
| Logic Blocks | — | 12 LABs of 4 macrocells each |
| Configuration Memory | — | Non-volatile UV-erasable EPROM |
| Programming Method | — | Altera programming hardware with MAX+PLUS II / legacy tools |
| Manufacturer | — | Rochester Electronics (licensed continuation of Altera / Intel PSG Classic EPLD line) |