EP1810JI-45 vs EP1810JC-35 Vergleich
Detaillierter Direktvergleich von EP1810JI-45 von Altera und EP1810JC-35 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP1810JI-45 | EP1810JC-35 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,75 | $5,48 |
| Manufacturer | Altera (now Intel FPGA) | — |
| Series | Classic EPLD Family | — |
| Device Type | UV-Erasable / OTP Complex PLD | UV-Erasable Complex PLD (UV PLD / CPLD) |
| Macrocell Count | 48 | — |
| Maximum Operating Frequency | 33.3 MHz | — |
| Propagation Delay (tPD) | 50 ns | — |
| Configurable I/O Lines | 48 | — |
| Dedicated Inputs | 12 | — |
| Technology | CMOS EPROM | — |
| Package Code | QCCJ | — |
| Package Type | 68-pin JLCC (J-leaded ceramic chip carrier) | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) |
| Terminal Form | J BEND | J-Bend |
| Package Shape | SQUARE | — |
| Number of Terminals | 68 | 68 |
| Temperature Grade | INDUSTRIAL | Commercial |
| Betriebstemperatur | -40 °C to +85 °C | — |
| Versorgungsspannung | 5 V (TTL compatible) | — |
| Programming Method | UV-erase (windowed) / OTP via JEDEC | — |
| Device Family | — | Classic EPLD (EP1810) |
| Number of Macrocells | — | 48 |
| Propagation Delay (tpd) | — | 35 ns (max) |
| Maximale Taktfrequenz | — | [DATA_NEEDED: fmax for this speed grade] |
| Process Technology | — | CMOS |
| Supply Voltage (Vcc) | — | 5 V (nominal) |
| Maximum Supply Voltage | — | 5.25 V (per distributor listing) |
| Betriebstemperaturbereich | — | 0°C to 70°C (Commercial) |
| Erasure Method | — | UV (quartz-windowed ceramic package) |
| RoHS-Status | — | Compliant (per Altera listing) |
| Lead-Free Status | — | Lead-free (per distributor listing) |
| Montageart | — | Surface Mount (J-Lead) |
| Logic Architecture | — | Programmable AND/OR array with macrocell outputs |