EP1810LC-20T vs EP1810LC-20 Vergleich
Detaillierter Direktvergleich von EP1810LC-20T von Intel und EP1810LC-20 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP1810LC-20T | EP1810LC-20 |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,95 | $7,85 |
| Family | Altera Classic EPLD | Classic EPLD |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 900 gates | 900 |
| Macrocells | 48 | 48 |
| Logic Array Blocks (LABs) | 4 x 12 macrocells | — |
| Maximum Toggle Frequency | 50 MHz | — |
| Pin-to-Pin Logic Delay (tPD) | 20 ns | — |
| Supply Voltage (VCC) | 5 V | — |
| Package Type | PLCC-68 (J-lead) | — |
| Montageart | Surface Mount (socket-compatible) | Surface Mount |
| Configuration Memory | On-chip EEPROM (non-volatile) | — |
| Programming Interface | JTAG (IEEE 1149.1) and Altera Master/Slave serial | — |
| Betriebstemperatur | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Shipping Format | Tape & Reel ("T" suffix) | — |
| RoHS-Status | Non-compliant (legacy 5V PLCC) | [DATA_NEEDED: rohs status] |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Maximum Operating Frequency | — | 50 MHz |
| Propagation Delay (tPD) | — | 20 ns |
| Versorgungsspannung | — | 5 V (4.75 V to 5.25 V) |
| Technology | — | CMOS EPROM |
| Programmability | — | UV-Erasable / OTP |
| Dedicated Inputs | — | 12 |
| Gehäuse | — | 68-pin PLCC |
| Package Suffix | — | LC (PLCC, windowed for UV erase on L variant) |
| Speed Grade | — | 20 ns (commercial) |