EP1810LC-20T vs EP1810LC-35T Vergleich
Detaillierter Direktvergleich von EP1810LC-20T von Intel und EP1810LC-35T von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP1810LC-20T | EP1810LC-35T |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,95 | $115,20 |
| Family | Altera Classic EPLD | — |
| Product Type | CPLD (Complex Programmable Logic Device) | Erasable Programmable Logic Device (EPLD) |
| Usable Gates | 900 gates | 900 |
| Macrocells | 48 | — |
| Logic Array Blocks (LABs) | 4 x 12 macrocells | — |
| Maximum Toggle Frequency | 50 MHz | — |
| Pin-to-Pin Logic Delay (tPD) | 20 ns | — |
| Supply Voltage (VCC) | 5 V | — |
| Package Type | PLCC-68 (J-lead) | — |
| Montageart | Surface Mount (socket-compatible) | Surface Mount (PLCC socket or direct solder) |
| Configuration Memory | On-chip EEPROM (non-volatile) | — |
| Programming Interface | JTAG (IEEE 1149.1) and Altera Master/Slave serial | — |
| Betriebstemperatur | 0C to +70C (commercial) | 0 C to +70 C (Commercial) |
| Shipping Format | Tape & Reel ("T" suffix) | — |
| RoHS-Status | Non-compliant (legacy 5V PLCC) | Non-compliant (legacy PLCC product) |
| Device Family | — | EP1810 Classic EPLD |
| Macro Cells | — | 48 |
| Pin-to-Pin Delay (tpd) | — | 35 ns |
| Maximum Frequency (fmax) | — | 28.6 MHz |
| Supply Voltage (Vcc) | — | 5 V |
| Technology | — | CMOS |
| Logic Compatibility | — | 100% TTL emulation |
| Gehäuse | — | 68-pin PLCC (Plastic Leaded Chip Carrier) |
| Package Suffix | — | T = Tape and Reel |
| Programming Method | — | UV-erasable (ceramic) / OTP (plastic); MAX+PLUS II |
| Logic Family Replacement Target | — | 74LS low-power Schottky TTL |