EP1810LC-20T vs EP1810LC-35T 比較
詳細な並列比較: EP1810LC-20T メーカー: Intel および EP1810LC-35T メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP1810LC-20T | EP1810LC-35T |
|---|---|---|
| ブランド | Intel | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.95 | $115.20 |
| Family | Altera Classic EPLD | — |
| Product Type | CPLD (Complex Programmable Logic Device) | Erasable Programmable Logic Device (EPLD) |
| Usable Gates | 900 gates | 900 |
| Macrocells | 48 | — |
| Logic Array Blocks (LABs) | 4 x 12 macrocells | — |
| Maximum Toggle Frequency | 50 MHz | — |
| Pin-to-Pin Logic Delay (tPD) | 20 ns | — |
| Supply Voltage (VCC) | 5 V | — |
| Package Type | PLCC-68 (J-lead) | — |
| 実装タイプ | Surface Mount (socket-compatible) | Surface Mount (PLCC socket or direct solder) |
| Configuration Memory | On-chip EEPROM (non-volatile) | — |
| Programming Interface | JTAG (IEEE 1149.1) and Altera Master/Slave serial | — |
| 動作温度 | 0C to +70C (commercial) | 0 C to +70 C (Commercial) |
| Shipping Format | Tape & Reel ("T" suffix) | — |
| RoHS ステータス | Non-compliant (legacy 5V PLCC) | Non-compliant (legacy PLCC product) |
| Device Family | — | EP1810 Classic EPLD |
| Macro Cells | — | 48 |
| Pin-to-Pin Delay (tpd) | — | 35 ns |
| Maximum Frequency (fmax) | — | 28.6 MHz |
| Supply Voltage (Vcc) | — | 5 V |
| Technology | — | CMOS |
| Logic Compatibility | — | 100% TTL emulation |
| パッケージ | — | 68-pin PLCC (Plastic Leaded Chip Carrier) |
| Package Suffix | — | T = Tape and Reel |
| Programming Method | — | UV-erasable (ceramic) / OTP (plastic); MAX+PLUS II |
| Logic Family Replacement Target | — | 74LS low-power Schottky TTL |