EP1810LI-35 vs EP1810JI-35 Vergleich

Detaillierter Direktvergleich von EP1810LI-35 von Altera und EP1810JI-35 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP1810LI-35 EP1810JI-35
Marke Altera Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $78,05 $18,60
Manufacturer Rochester Electronics, LLC (original Altera design) —
Part Family Altera Classic EPLD —
Device Type Erasable Programmable Logic Device (EPLD) —
Macrocells 48 48
Propagation Delay (tPD) 35 ns —
Speed Grade 35 (slowest in EP1810L family) -35
Gehäuse 68-pin PLCC (J-Lead, plastic) 28-pin JLCC (J-leaded ceramic, windowed)
Pin/Package Code PLCC-68 / PQCC68 —
Technology CMOS, UV-erasable EPROM configuration cell —
Versorgungsspannung 5 V (TTL-compatible I/O) 5 V (typical classic EPLD)
Betriebstemperatur -40 C to +85 C (industrial, 'I' suffix) -40C to +85C (Industrial)
Montageart Surface Mount (PLCC socket compatible) Through-Hole (J-lead)
JTAG Boundary Scan IEEE 1149.1 compliant —
Logic Elements Logic Array Blocks (LABs) connected via Programmable Interconnect Array (PIA) —
RoHS-Status [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC]
Lead-Free [DATA_NEEDED: lead-free status] —
MSL-Level [DATA_NEEDED: MSL rating] [DATA_NEEDED: MSL rating]
Device Family — Classic EPLD
Logic Array Blocks — 8 LABs of 16 macrocells
Dedicated Inputs — 48
Pin-to-Pin Propagation Delay (tPD) — 35 ns
Process Technology — CMOS EPROM (UV-erasable)
Programmability — UV-erase, windowed for lab reprogram
Programming Interface — JEDEC fuse file via legacy programmer

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