EP1810LI-35 vs EP1810JI-35 比較
詳細な並列比較: EP1810LI-35 メーカー: Altera および EP1810JI-35 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP1810LI-35 | EP1810JI-35 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $78.05 | $18.60 |
| Manufacturer | Rochester Electronics, LLC (original Altera design) | — |
| Part Family | Altera Classic EPLD | — |
| Device Type | Erasable Programmable Logic Device (EPLD) | — |
| Macrocells | 48 | 48 |
| Propagation Delay (tPD) | 35 ns | — |
| Speed Grade | 35 (slowest in EP1810L family) | -35 |
| パッケージ | 68-pin PLCC (J-Lead, plastic) | 28-pin JLCC (J-leaded ceramic, windowed) |
| Pin/Package Code | PLCC-68 / PQCC68 | — |
| Technology | CMOS, UV-erasable EPROM configuration cell | — |
| 電源電圧 | 5 V (TTL-compatible I/O) | 5 V (typical classic EPLD) |
| 動作温度 | -40 C to +85 C (industrial, 'I' suffix) | -40C to +85C (Industrial) |
| 実装タイプ | Surface Mount (PLCC socket compatible) | Through-Hole (J-lead) |
| JTAG Boundary Scan | IEEE 1149.1 compliant | — |
| Logic Elements | Logic Array Blocks (LABs) connected via Programmable Interconnect Array (PIA) | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| MSLレベル | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL rating] |
| Device Family | — | Classic EPLD |
| Logic Array Blocks | — | 8 LABs of 16 macrocells |
| Dedicated Inputs | — | 48 |
| Pin-to-Pin Propagation Delay (tPD) | — | 35 ns |
| Process Technology | — | CMOS EPROM (UV-erasable) |
| Programmability | — | UV-erase, windowed for lab reprogram |
| Programming Interface | — | JEDEC fuse file via legacy programmer |