EP1810LI-35 vs EP1810LI-25 Vergleich

Detaillierter Direktvergleich von EP1810LI-35 von Altera und EP1810LI-25 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP1810LI-35 EP1810LI-25
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $78,05 $9,95
Manufacturer Rochester Electronics, LLC (original Altera design) —
Part Family Altera Classic EPLD —
Device Type Erasable Programmable Logic Device (EPLD) EPLD (Erasable Programmable Logic Device), UV-erasable / OTP
Macrocells 48 48
Propagation Delay (tPD) 35 ns 25 ns
Speed Grade 35 (slowest in EP1810L family) —
Gehäuse 68-pin PLCC (J-Lead, plastic) 68-pin PLCC (J68, J-Lead)
Pin/Package Code PLCC-68 / PQCC68 —
Technology CMOS, UV-erasable EPROM configuration cell —
Versorgungsspannung 5 V (TTL-compatible I/O) —
Betriebstemperatur -40 C to +85 C (industrial, 'I' suffix) —
Montageart Surface Mount (PLCC socket compatible) —
JTAG Boundary Scan IEEE 1149.1 compliant —
Logic Elements Logic Array Blocks (LABs) connected via Programmable Interconnect Array (PIA) —
RoHS-Status [DATA_NEEDED: RoHS compliance status] unknown
Lead-Free [DATA_NEEDED: lead-free status] —
MSL-Level [DATA_NEEDED: MSL rating] —
Family — Altera Classic EPLD
Usable Gates — 900
Maximum Counter Frequency — 40 MHz
Supply Voltage (VCC) — 4.5 V to 5.5 V (nominal 5 V)
I/O Pins — 48
Dedicated Inputs — 12
Global Clock Inputs — 4
Interconnect — Programmable global and local buses
JESD-30 Package Code — S-PQCC-J68
Process Technology — CMOS
Operating Temperature (Industrial 'I' suffix) — -40 C to +85 C
Programming Mode — EPROM/UV-erasable (windowed) and OTP
Development Tool — Altera MAX+PLUS II
Lead-Free Status — unknown

Datenblätter & Ressourcen

Alle Produkte durchsuchen BOM erstellen Angebot anfordern