EP1810LI-35 vs EP1810LI-25 Comparaison
Comparaison détaillée côte à côte de EP1810LI-35 par Altera et EP1810LI-25 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP1810LI-35 | EP1810LI-25 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $78,05 | $9,95 |
| Manufacturer | Rochester Electronics, LLC (original Altera design) | — |
| Part Family | Altera Classic EPLD | — |
| Device Type | Erasable Programmable Logic Device (EPLD) | EPLD (Erasable Programmable Logic Device), UV-erasable / OTP |
| Macrocells | 48 | 48 |
| Propagation Delay (tPD) | 35 ns | 25 ns |
| Speed Grade | 35 (slowest in EP1810L family) | — |
| Boîtier | 68-pin PLCC (J-Lead, plastic) | 68-pin PLCC (J68, J-Lead) |
| Pin/Package Code | PLCC-68 / PQCC68 | — |
| Technology | CMOS, UV-erasable EPROM configuration cell | — |
| Tension d'alimentation | 5 V (TTL-compatible I/O) | — |
| Température de fonctionnement | -40 C to +85 C (industrial, 'I' suffix) | — |
| Type de montage | Surface Mount (PLCC socket compatible) | — |
| JTAG Boundary Scan | IEEE 1149.1 compliant | — |
| Logic Elements | Logic Array Blocks (LABs) connected via Programmable Interconnect Array (PIA) | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Niveau MSL | [DATA_NEEDED: MSL rating] | — |
| Family | — | Altera Classic EPLD |
| Usable Gates | — | 900 |
| Maximum Counter Frequency | — | 40 MHz |
| Supply Voltage (VCC) | — | 4.5 V to 5.5 V (nominal 5 V) |
| I/O Pins | — | 48 |
| Dedicated Inputs | — | 12 |
| Global Clock Inputs | — | 4 |
| Interconnect | — | Programmable global and local buses |
| JESD-30 Package Code | — | S-PQCC-J68 |
| Process Technology | — | CMOS |
| Operating Temperature (Industrial 'I' suffix) | — | -40 C to +85 C |
| Programming Mode | — | EPROM/UV-erasable (windowed) and OTP |
| Development Tool | — | Altera MAX+PLUS II |
| Lead-Free Status | — | unknown |