EP1K100QI208-3 vs EP1K100QI208-2 Vergleich

Detaillierter Direktvergleich von EP1K100QI208-3 von Altera und EP1K100QI208-2 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP1K100QI208-3 EP1K100QI208-2
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete NRND
Lagerstatus In Stock In Stock
Stückpreis (USD) $19,75 $23,90
Family ACEX 1K (FLEX 10K) ACEX-1K
Logic Cells 4,992 —
Configurable Logic Blocks (CLBs) 624 —
Approximate System Gates 100,000 —
User I/O Pins 147 —
Dedicated Inputs 6 —
Core Supply Voltage (VCCINT) 2.5 V nominal (max 2.625 V) —
I/O Supply Voltage (VCCIO) [DATA_NEEDED: VCCIO min/max range] —
Speed Grade -3 (fastest) —
Betriebstemperatur -40 °C to +85 °C (industrial) -40C to +85C (Industrial)
Gehäuse 208-pin PQFP (QFP, gull-wing) 208-pin PQFP (BFQFP)
Terminal Count 208 —
Terminal Form Gull Wing —
Package Code QFP (Power Quad Flat Pack) —
Montageart Surface Mount Surface Mount
Configuration Method SRAM, serial/parallel (EPC2/EPC4 supported) —
Embedded Memory EAB blocks (RAM/ROM/multiplier) —
RoHS-Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance status]
Logic Elements — 4,992 cells
System Gates — 100,000
Logic Array Blocks (LABs) — 624
Embedded Memory (EAB) — 49,152 bits
User I/Os — 147
Maximum Operating Frequency — 250 MHz
Core Voltage (VCCINT) — 2.5 V
Process Technology — 0.22 umm CMOS SRAM
Pitch — 0.5 mm
Configuration Interface — JTAG (IEEE 1149.1) / serial / EPC2
Global Clock Networks — 4
I/O Standards Supported — LVTTL, LVCMOS, PCI, 5V tolerant

Datenblätter & Ressourcen

Alle Produkte durchsuchen BOM erstellen Angebot anfordern