EP1K30QI208-2 vs EP1K30QC208-1 Vergleich
Detaillierter Direktvergleich von EP1K30QI208-2 von Altera und EP1K30QC208-1 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP1K30QI208-2 | EP1K30QC208-1 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,00 | $10,85 |
| Product Category | FPGA - Field Programmable Gate Array | — |
| Series | ACEX-1K | — |
| Number of Logic Elements/Cells | 1,728 | — |
| Total RAM Bits | 24,576 | — |
| Number of User I/Os | 147 | — |
| Number of Typical Gates | 30,000 | — |
| Core Supply Voltage | 2.5 V | — |
| Maximale Taktfrequenz | 200 MHz | — |
| Speed Grade | -2 | — |
| Gehäuse / Bauform | 208-BFQFP (PQFP-208) | — |
| Package Code | FQFP | — |
| Package Shape | SQUARE | — |
| Terminal Form | GULL WING | — |
| Number of Terminals | 208 | — |
| Temperature Grade | Industrial (I) | — |
| Montageart | Surface Mount | Surface Mount (gull-wing leads) |
| Betriebstemperaturbereich | [DATA_NEEDED: exact operating temperature range in degrees C] | — |
| Propagation Delay | 0.4 ns (per AiPCBA programming manual summary) | — |
| Memory Features | Enhanced embedded array with dual-port SRAM support | — |
| Supported I/O Standards | [DATA_NEEDED: supported I/O standards] | — |
| Configuration Device | [DATA_NEEDED: required configuration device] | — |
| RoHS-Status | [DATA_NEEDED: RoHS status for non-N variant] | Compliant (lead-free) |
| Device Family | — | ACEX-1K |
| Logic Elements (LEs) | — | 1,728 |
| Equivalent Gates | — | 30,000 |
| Logic Array Blocks (LABs) | — | 216 |
| Embedded Memory (EAB) | — | 24,576 bits |
| Maximum User I/O | — | 147 |
| Core Supply Voltage (VCCINT) | — | 2.5 V (2.375 V to 2.625 V) |
| Gehäuse | — | 208-BFQFP (Plastic Quad Flat Pack, PQFP208) |
| Terminal Pitch | — | 0.500 mm |
| Betriebstemperatur | — | 0 °C to +70 °C (commercial) |
| Maximum Operating Frequency | — | up to 250 MHz (family typical) |
| Process Technology | — | 2.5 V CMOS |
| Configuration Method | — | SRAM, in-system reconfigurable (volatile) |
| Boundary-Scan Test | — | JTAG IEEE 1149.1 |
| I/O Voltage Support | — | 2.5 V / 3.3 V (multi-volt I/O) |
| Configuration Device Support | — | EPC2, EPC4, EPC8 Enhanced Configuration Devices |