EP1K50FC256-1 vs EP1K50FC256-2 Vergleich

Detaillierter Direktvergleich von EP1K50FC256-1 von Altera und EP1K50FC256-2 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP1K50FC256-1 EP1K50FC256-2
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $18,95 $62,00
Family ACEX 1K ACEX 1K Family
Logic Elements / Cells 2,880 —
System Gates 50,000 —
Maximum System Gates 199,000 —
Logic Array Blocks (LABs) 360 —
Embedded Memory (EAB) 40 Kbit (EAB-based) —
Total RAM Bits 40,960 40,960
User I/Os 186 186
Number of I/O Banks [DATA_NEEDED: number of I/O banks] —
Operating Supply Voltage (Core) 2.5 V (2.375 V to 2.625 V) —
Process Technology 0.22 µm CMOS 0.22 µm CMOS
Maximum Internal Frequency 250 MHz —
Configuration Memory Type SRAM —
Gehäuse 256-ball FBGA (FineLine BGA) —
Montageart Surface Mount Surface Mount
Operating Temperature Grade Commercial (0 °C to +70 °C) —
RoHS-Status Non-compliant (per distributor data) Compliant
Part Status Obsolete (per Arrow listing) —
Series — ACEX-1K
Logic Cells / Elements — 2,880
Typical Gates — 50,000
Number of LABs/CLBs — 360
Number of Gates — 50,000
Voltage - Supply — 2.375 V to 2.625 V (nominal 2.5 V)
Propagation Delay — 0.4 ns (per Partstack listing)
Betriebstemperatur — 0°C to +70°C (commercial)
Gehäuse / Bauform — 256-BGA (FineLine BGA, 17x17 mm)
Montagestil — SMD/SMT
Programming Type — In-System Programmable via JTAG (IEEE 1149.1)
Configuration Method — SRAM-based, volatile configuration
REACH Status — Compliant
MSL-Level — [DATA_NEEDED: MSL level]

Datenblätter & Ressourcen

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