EP1K50FC256-1 vs EP1K50FC256-2 对比

详细并排对比 EP1K50FC256-1 出自 Altera 和 EP1K50FC256-2 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1K50FC256-1 EP1K50FC256-2
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $18.95 $62.00
Family ACEX 1K ACEX 1K Family
Logic Elements / Cells 2,880 —
System Gates 50,000 —
Maximum System Gates 199,000 —
Logic Array Blocks (LABs) 360 —
Embedded Memory (EAB) 40 Kbit (EAB-based) —
Total RAM Bits 40,960 40,960
User I/Os 186 186
Number of I/O Banks [DATA_NEEDED: number of I/O banks] —
Operating Supply Voltage (Core) 2.5 V (2.375 V to 2.625 V) —
Process Technology 0.22 µm CMOS 0.22 µm CMOS
Maximum Internal Frequency 250 MHz —
Configuration Memory Type SRAM —
封装 256-ball FBGA (FineLine BGA) —
安装类型 Surface Mount Surface Mount
Operating Temperature Grade Commercial (0 °C to +70 °C) —
RoHS 状态 Non-compliant (per distributor data) Compliant
Part Status Obsolete (per Arrow listing) —
Series — ACEX-1K
Logic Cells / Elements — 2,880
Typical Gates — 50,000
Number of LABs/CLBs — 360
Number of Gates — 50,000
Voltage - Supply — 2.375 V to 2.625 V (nominal 2.5 V)
Propagation Delay — 0.4 ns (per Partstack listing)
工作温度 — 0°C to +70°C (commercial)
封装 / 外壳 — 256-BGA (FineLine BGA, 17x17 mm)
安装方式 — SMD/SMT
Programming Type — In-System Programmable via JTAG (IEEE 1149.1)
Configuration Method — SRAM-based, volatile configuration
REACH Status — Compliant
MSL 等级 — [DATA_NEEDED: MSL level]

数据手册与资源

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