EP1K50TC144-2N vs EP1K50TC144-1 Vergleich

Detaillierter Direktvergleich von EP1K50TC144-2N von Altera und EP1K50TC144-1 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP1K50TC144-2N EP1K50TC144-1
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus NRND NRND
Lagerstatus In Stock In Stock
Stückpreis (USD) $22,45 $9,95
Series ACEX-1K —
Family ACEX 1K Device Family (2.5 V) ACEX-1K
Typical Gates 50,000 —
Maximum Gates 100,000 —
Logic Elements (Cells) 2,880 —
Logic Array Blocks (LABs) 360 360
Embedded Memory (EAB) 40,960 bits (12 EABs x 4,096 bits) —
User I/Os 102 —
Anzahl der Pins 144 —
Gehäuse TQFP-144 (144-LQFP), 22 x 22 mm, 0.5 mm pitch 144-pin LQFP (TQFP)
Core Voltage (VCCINT) 2.5 V —
I/O Voltage (VCCIO) 2.5 V / 3.3 V (multi-standard) —
Process Technology 0.22 µm CMOS CMOS
Internal Frequency Up to 200 MHz —
Propagation Delay (speed grade) 0.4 ns nominal (speed grade -2) —
Operating Temperature Grade Commercial (suffix N) Commercial
Montageart Surface Mount Surface Mount (Gull-Wing Leads)
Configuration Serial, JTAG, supported configuration devices (EPC, EPC2) —
RoHS-Status [DATA_NEEDED: rohs status] —
Lead-Free [DATA_NEEDED: lead-free status] —
Logic Elements / Cells — 2,880
System Gates — 50,000
Embedded Memory (Bits) — 40,960
User I/O Pins — 102
Core Voltage — 2.5 V
I/O Voltage — 2.5 V (5-V tolerant I/O)
Maximum Internal Frequency — 250 MHz
Embedded Array Blocks (EABs) — Dual-port, configurable as RAM/ROM
Programming Interface — JTAG (IEEE 1149.1) + serial configuration
Development Tools — MAX+PLUS II, Quartus
Lead-Free / RoHS — [DATA_NEEDED: Lead-free / RoHS status]
MSL-Level — [DATA_NEEDED: MSL moisture sensitivity level]

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