EP1M350F78016 vs EP1M350F780C6N Vergleich
Detaillierter Direktvergleich von EP1M350F78016 von Intel und EP1M350F780C6N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP1M350F780C6N - Mercury 350K FPGA, 486 I/O, 780-BGA | Intel (Altera)
EP1M350F780C6N ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EP1M350F78016 | EP1M350F780C6N |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $155,00 | $219,40 |
| Family | Mercury PLD | Mercury (EP1M350) |
| Device Type | FPGA (Field Programmable Gate Array) | Loadable Programmable Logic Device (PLD) / FPGA |
| User I/O Count | 486 | — |
| Gehäuse | 780-ball FCBGA (FineLine BGA) | 780-ball FC-FBGA (FINE LINE BGA-780) |
| Logic Element Architecture | 4-input LUT-based CLB | — |
| Embedded Memory | Yes (memory blocks) | — |
| Configuration Interface | JTAG (IEEE 1149.1) + serial/parallel passive | JTAG (IEEE 1149.1) / passive serial |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL+, HSTL, SSTL | — |
| Betriebstemperatur | Industrial (-40C to +85C) | 0 C to 85 C |
| Speed Grade | -16 | — |
| Core Voltage | [DATA_NEEDED: core voltage] | — |
| Process Technology | Sub-micron CMOS | — |
| Montageart | Surface Mount (BGA) | — |
| RoHS-Status | Compliant | [DATA_NEEDED: rohs_status] |
| Configuration Memory Support | Enhanced configuration device / passive serial | — |
| JTAG Boundary Scan | Yes (IEEE 1149.1) | — |
| Original Manufacturer | Altera Corporation (now Intel Programmable Solutions Group) | — |
| Logic Family | — | CMOS, SRAM-based LUT |
| System Gates | — | 350,000 |
| Logic Cells / Elements | — | 14,400 |
| User I/Os | — | 486 |
| Integrated Transceivers | — | Yes, with CDR up to 1.25 Gbps |
| Core Supply Voltage | — | 1.8 V |
| Terminal Form | — | Ball |
| Package Code (JEDEC) | — | S-PBGA-B780 |
| MSL-Level | — | [DATA_NEEDED: msl_level] |
| Lead-Free | — | [DATA_NEEDED: lead_free] |
| Architecture | — | Look-up table (LUT)-based, optimized for high-speed serial I/O |
| Total Package Pins / Balls | — | 780 |