EP1M350F78016 vs EP1M350F780C6N Comparaison
Comparaison détaillée côte à côte de EP1M350F78016 par Intel et EP1M350F780C6N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EP1M350F780C6N - Mercury 350K FPGA, 486 I/O, 780-BGA | Intel (Altera)
EP1M350F780C6N ⚠ Dernier achatComparaison des spécifications
| Paramètre | EP1M350F78016 | EP1M350F780C6N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $155,00 | $219,40 |
| Family | Mercury PLD | Mercury (EP1M350) |
| Device Type | FPGA (Field Programmable Gate Array) | Loadable Programmable Logic Device (PLD) / FPGA |
| User I/O Count | 486 | — |
| Boîtier | 780-ball FCBGA (FineLine BGA) | 780-ball FC-FBGA (FINE LINE BGA-780) |
| Logic Element Architecture | 4-input LUT-based CLB | — |
| Embedded Memory | Yes (memory blocks) | — |
| Configuration Interface | JTAG (IEEE 1149.1) + serial/parallel passive | JTAG (IEEE 1149.1) / passive serial |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL+, HSTL, SSTL | — |
| Température de fonctionnement | Industrial (-40C to +85C) | 0 C to 85 C |
| Speed Grade | -16 | — |
| Core Voltage | [DATA_NEEDED: core voltage] | — |
| Process Technology | Sub-micron CMOS | — |
| Type de montage | Surface Mount (BGA) | — |
| Statut RoHS | Compliant | [DATA_NEEDED: rohs_status] |
| Configuration Memory Support | Enhanced configuration device / passive serial | — |
| JTAG Boundary Scan | Yes (IEEE 1149.1) | — |
| Original Manufacturer | Altera Corporation (now Intel Programmable Solutions Group) | — |
| Logic Family | — | CMOS, SRAM-based LUT |
| System Gates | — | 350,000 |
| Logic Cells / Elements | — | 14,400 |
| User I/Os | — | 486 |
| Integrated Transceivers | — | Yes, with CDR up to 1.25 Gbps |
| Core Supply Voltage | — | 1.8 V |
| Terminal Form | — | Ball |
| Package Code (JEDEC) | — | S-PBGA-B780 |
| Niveau MSL | — | [DATA_NEEDED: msl_level] |
| Lead-Free | — | [DATA_NEEDED: lead_free] |
| Architecture | — | Look-up table (LUT)-based, optimized for high-speed serial I/O |
| Total Package Pins / Balls | — | 780 |