EP1M350F780I7N vs EP1M350F780C6N Vergleich

Detaillierter Direktvergleich von EP1M350F780I7N von Altera und EP1M350F780C6N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Intel
EP1M350F780C6N EP1M350F780C6N - Mercury 350K FPGA, 486 I/O, 780-BGA | Intel (Altera)

EP1M350F780C6N - Mercury 350K FPGA, 486 I/O, 780-BGA | Intel (Altera)

EP1M350F780C6N ⚠ Letzte Bestellmöglichkeit

Spezifikationsvergleich

Parameter EP1M350F780I7N EP1M350F780C6N
Marke Altera Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Letzte Kaufgelegenheit
Lagerstatus In Stock In Stock
Stückpreis (USD) $152,25 $219,40
Device Family Mercury PLD (Enhanced Configuration Device) —
Funktion Configuration device for SRAM-based LUT FPGAs —
Gehäuse 780-ball FineLine BGA 780-ball FC-FBGA (FINE LINE BGA-780)
Speed Grade 7 —
Betriebstemperaturbereich -40C to +100C (Industrial, I suffix) —
Configuration Modes Serial and parallel FPGA configuration —
Programming Interface JTAG (IEEE 1149.1) boundary-scan —
On-chip Memory Flash memory array —
Configuration Controller Integrated state-machine controller —
Bitstream Support CRC-validated, compression-compatible —
Montageart Surface Mount (BGA) —
MSL-Level [DATA_NEEDED: MSL rating] [DATA_NEEDED: msl_level]
RoHS-Status [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: rohs_status]
Lead-Free [DATA_NEEDED: lead-free status] [DATA_NEEDED: lead_free]
Configuration Compatibility High-density SRAM-based LUT FPGAs (Stratix and equivalent) —
Family — Mercury (EP1M350)
Device Type — Loadable Programmable Logic Device (PLD) / FPGA
Logic Family — CMOS, SRAM-based LUT
System Gates — 350,000
Logic Cells / Elements — 14,400
User I/Os — 486
Integrated Transceivers — Yes, with CDR up to 1.25 Gbps
Core Supply Voltage — 1.8 V
Terminal Form — Ball
Package Code (JEDEC) — S-PBGA-B780
Betriebstemperatur — 0 C to 85 C
Configuration Interface — JTAG (IEEE 1149.1) / passive serial
Architecture — Look-up table (LUT)-based, optimized for high-speed serial I/O
Total Package Pins / Balls — 780

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