EP1S10F672C7 vs EP1S10F672C7N Vergleich
Detaillierter Direktvergleich von EP1S10F672C7 von Altera und EP1S10F672C7N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP1S10F672C7 | EP1S10F672C7N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $158,00 | $171,00 |
| Family | Stratix | — |
| Logic Elements | 10,570 | — |
| Embedded Memory | 920,448 bits | — |
| User I/Os | 345 | — |
| Gehäuse | 672-pin FBGA (FineLine BGA) | — |
| Package Dimensions | 35 x 35 mm, 1.27 mm pitch | — |
| Process Technology | 130 nm CMOS | 130 nm CMOS |
| Core Voltage (VCCINT) | 1.5 V | — |
| Logic Cells | 10,570 | — |
| LABs (Logic Array Blocks) | 1,057 | — |
| Betriebstemperatur | 0 C to 85 C (Commercial) | 0C to +85C (Commercial) |
| Montageart | Surface Mount | Surface Mount |
| I/O Standards | LVTTL, LVCMOS, LVDS, SSTL, HSTL | — |
| Configuration Mode | JTAG, Passive Serial, Active Serial | — |
| RoHS-Status | unknown | [DATA_NEEDED: RoHS compliance] |
| Series | — | Stratix |
| Logic Elements / Cells | — | 10,570 |
| Number of LABs/CLBs | — | 1,057 |
| Total RAM Bits | — | 920,448 |
| Number of User I/Os | — | 345 |
| Number of Gates | — | [DATA_NEEDED: total gate count] |
| DSP Blocks | — | 6 |
| Package Type | — | 672-BBGA (FBGA) 35 x 35 mm, 1.27 mm pitch |
| Core Voltage | — | 1.5 V |
| Maximum Operating Frequency | — | 420.17 MHz |
| Configuration Method | — | SRAM, JTAG, passive/active serial/parallel |
| MSL-Level | — | [DATA_NEEDED: MSL moisture sensitivity level] |