EP1S10F672I7N vs EP1S10F672C7 Vergleich
Detaillierter Direktvergleich von EP1S10F672I7N von Intel und EP1S10F672C7 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP1S10F672I7N - Stratix FPGA, 10,570 LEs, 672-BGA | Intel
EP1S10F672I7N ⚠ Letzte Bestellmöglichkeit
Spezifikationsvergleich
| Parameter | EP1S10F672I7N | EP1S10F672C7 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $118,00 | $158,00 |
| Family | Stratix | Stratix |
| Logic Elements | 10,570 | 10,570 |
| Logic Array Blocks (LABs) | 1,057 | — |
| User I/Os | 345 | 345 |
| Process Technology | 130 nm CMOS | 130 nm CMOS |
| Core Supply Voltage | 1.5 V | — |
| Maximum Internal Frequency | 420.17 MHz | — |
| Betriebstemperatur | 0C to 85C | 0 C to 85 C (Commercial) |
| Gehäuse | 672-ball FineLine BGA, 35 x 35 mm, 1.27 mm pitch | 672-pin FBGA (FineLine BGA) |
| Logic Family | CMOS | — |
| Embedded Memory | 920 Kbits (TriMatrix) | 920,448 bits |
| DSP Blocks | Yes (dedicated) | — |
| Configuration Interface | Active Serial / Passive Serial / JTAG | — |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Speed Grade | I7 (industrial, -7 speed bin) | — |
| MSL-Level | 3 (per JEDEC J-STD-020, typical for BGA of this era) | — |
| Montageart | Surface Mount (BGA) | Surface Mount |
| RoHS-Status | [DATA_NEEDED: per Intel PDN] | unknown |
| Package Dimensions | — | 35 x 35 mm, 1.27 mm pitch |
| Core Voltage (VCCINT) | — | 1.5 V |
| Logic Cells | — | 10,570 |
| LABs (Logic Array Blocks) | — | 1,057 |
| I/O Standards | — | LVTTL, LVCMOS, LVDS, SSTL, HSTL |
| Configuration Mode | — | JTAG, Passive Serial, Active Serial |