EP1S20F672I7 vs EP1S20F672C7N Vergleich
Detaillierter Direktvergleich von EP1S20F672I7 von Intel und EP1S20F672C7N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP1S20F672I7 - Stratix FPGA, 18,460 LEs, 672-BGA | Intel / Altera
EP1S20F672I7 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EP1S20F672I7 | EP1S20F672C7N |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $199,50 | $109,20 |
| Family | Stratix (first generation) | Stratix |
| Logic Elements (LEs) | 18,460 | 18,460 |
| Maximum RAM Bits | 1,669,248 | — |
| DSP Blocks | [DATA_NEEDED: exact DSP block count] | 56 (dedicated 18x18 multipliers) |
| Maximum User I/Os | 426 | — |
| Supply Voltage (VCCINT core) | 1.5 V | — |
| Logic Family | CMOS | — |
| Gehäuse | 672-BBGA (FineLine BGA), 35 x 35 mm, 1.27 mm pitch | 672-FBGA (FineLine BGA) |
| Betriebstemperatur | -40C to +85C (industrial grade, I7 suffix) | 0°C to +85°C (commercial) |
| Configuration Modes | Passive Serial, Passive Parallel, JTAG | PS, PPS, FPP, JTAG |
| Number of Pins / Balls | 672 | — |
| Montageart | Surface Mount (BGA) | Surface Mount |
| Clock Management PLLs | [DATA_NEEDED: PLL count] | — |
| RoHS-Status | unknown | — |
| Lead-Free / Finish | SnPb (e0 per Partstack datasheet extract) | — |
| MSL-Level | unknown | [DATA_NEEDED: moisture sensitivity level] |
| Status | Last Time Buy (per distributor notices) | — |
| Series | — | Stratix (first generation) |
| Logic Cells | — | 18,460 |
| Configurable Logic Blocks (CLBs) | — | 2,132 |
| Embedded Memory (TriMatrix) | — | 1,669,248 bits (426 Kbit total) |
| Maximum User I/O | — | 586 |
| I/O Banks | — | [DATA_NEEDED: I/O bank count] |
| PLLs | — | Up to 12 |
| Maximum Operating Frequency | — | 420.17 MHz |
| Core Voltage | — | 1.5 V |
| Process Technology | — | 130 nm CMOS |
| Package Body Size | — | 35 mm x 35 mm |
| Ball Pitch | — | 1.27 mm |
| Speed Grade | — | C7 (-7) |
| Lead-Free / RoHS | — | Yes (lead-free finish, RoHS compliant) |