EP1S25F672C5N vs EP1S25F672C6 Vergleich
Detaillierter Direktvergleich von EP1S25F672C5N von Intel und EP1S25F672C6 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP1S25F672C6 - Stratix FPGA 25,660 LE | Intel | BGA-672
EP1S25F672C6 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EP1S25F672C5N | EP1S25F672C6 |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $142,00 | $125,00 |
| Family | Stratix | Stratix |
| Series | EP1S25 | — |
| Logic Elements (Cells) | 25,660 | — |
| Number of CLBs | 2,566 | — |
| Number of Logic Cells / Gates | [DATA_NEEDED: total system gates] | — |
| Process Technology | 130 nm CMOS | 130 nm CMOS |
| Maximum Internal Frequency | 500 MHz | — |
| Core Supply Voltage | 1.5 V (nominal) | — |
| Number of I/O Pins | 473 user I/O | — |
| Number of I/O Banks | [DATA_NEEDED: I/O bank count] | — |
| Package Type | FineLine BGA (FBGA) | — |
| Package Pin Count | 672 | — |
| Ball Pitch | 1.00 mm | — |
| Betriebstemperaturbereich | 0 °C to +85 °C (commercial) | — |
| Speed Grade | C5 | 6 |
| Lead-Free (Pb-Free) | Yes (suffix "N") | — |
| Configuration Method | SRAM-based, programmable via JTAG / Passive Serial / Fast Passive Parallel | JTAG, Passive Serial, Fast Passive Parallel, Active Serial |
| Montageart | Surface Mount (BGA) | Surface Mount |
| RoHS-Status | Compliant | Compliant |
| Logic Elements | — | 25,660 |
| Configurable Logic Blocks (CLBs) | — | 2,852 |
| Total RAM Bits | — | 1,944,576 |
| DSP Blocks | — | 14 |
| Maximum User I/O | — | 473 |
| Gehäuse | — | 672-BBGA (FineLine BGA, 35 x 35 mm, 1.27 mm pitch) |
| Core Voltage | — | 1.5 V |
| Betriebstemperatur | — | 0C to +85C (Commercial) |
| Logic Family | — | CMOS |
| PLL Count (Maximum) | — | 12 (including enhanced PLLs) |