EP1S25F672C7N vs EP1S20F672C7N Vergleich

Detaillierter Direktvergleich von EP1S25F672C7N von Altera und EP1S20F672C7N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP1S25F672C7N EP1S20F672C7N
Marke Altera Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $535,00 $109,20
Device Family Stratix —
Logic Elements (LEs) 25,660 18,460
Logic Array Blocks (LABs) 2,566 —
Embedded Memory Bits 1,944,576 —
Maximum User I/O 473 586
Number of I/O Pins 672 (BGA balls) —
Gehäuse 672-BBGA (FineLine BGA), 35 × 35 mm, 1.27 mm pitch 672-FBGA (FineLine BGA)
Process Technology 0.13 µm CMOS 130 nm CMOS
Core Supply Voltage (VCCINT) 1.5 V —
I/O Supply Voltage (VCCIO) [DATA_NEEDED: bank-dependent 1.2 V–3.3 V] —
Betriebstemperatur 0 °C to 85 °C (commercial) 0°C to +85°C (commercial)
Montageart Surface Mount Surface Mount
Configuration Method JTAG / Passive Serial / Active Serial —
MSL-Level [DATA_NEEDED: MSL rating] [DATA_NEEDED: moisture sensitivity level]
RoHS-Status [DATA_NEEDED: confirm from product page] —
Series — Stratix (first generation)
Family — Stratix
Logic Cells — 18,460
Configurable Logic Blocks (CLBs) — 2,132
Embedded Memory (TriMatrix) — 1,669,248 bits (426 Kbit total)
DSP Blocks — 56 (dedicated 18x18 multipliers)
I/O Banks — [DATA_NEEDED: I/O bank count]
PLLs — Up to 12
Maximum Operating Frequency — 420.17 MHz
Core Voltage — 1.5 V
Package Body Size — 35 mm x 35 mm
Ball Pitch — 1.27 mm
Speed Grade — C7 (-7)
Lead-Free / RoHS — Yes (lead-free finish, RoHS compliant)
Configuration Modes — PS, PPS, FPP, JTAG

Datenblätter & Ressourcen

Alle Produkte durchsuchen BOM erstellen Angebot anfordern