EP1S25F780C5N vs EP1S25F780I6 Vergleich
Detaillierter Direktvergleich von EP1S25F780C5N von Intel und EP1S25F780I6 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP1S25F780C5N | EP1S25F780I6 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $595,00 | $162,00 |
| Family | Stratix | Stratix |
| Logic Elements | 25,660 | — |
| Logic Array Blocks (LABs) | 2,566 | — |
| Maximum User I/O | 597 | — |
| Gehäuse | 780-ball FBGA, 29 x 29 mm, 1.0 mm pitch | 780-ball FBGA (FineLine BGA, 29 x 29 mm, 1 mm pitch) |
| Process Technology | 130 nm CMOS | — |
| Core Supply Voltage | 1.5 V | — |
| Betriebstemperatur | 0 C to 85 C (Commercial Extended) | 0 °C to +85 °C (Industrial, -I6 grade) |
| Embedded Memory | TriMatrix memory blocks, up to ~1.92 Mbits total | — |
| DSP Blocks | Dedicated multiplier/accumulator blocks | 28 |
| PLLs | 4 | — |
| I/O Banks | 12 | — |
| Maximum Frequency (internal) | up to 500 MHz logic, 420 MHz DSP | — |
| Supported I/O Standards | LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, PCI, PCI-X | — |
| Configuration Modes | Passive Serial, Passive Parallel Sync/Async, JTAG | — |
| RoHS-Status | [DATA_NEEDED: confirm per specific reel lot] | [DATA_NEEDED: RoHS compliance status] |
| Montageart | Surface Mount (BGA) | Surface Mount (BGA) |
| MSL-Level | [DATA_NEEDED: MSL rating per JEDEC J-STD-020] | [DATA_NEEDED: MSL rating] |
| Logic Elements (LE) | — | 25,660 |
| Logic Array Blocks (LAB) | — | 2,566 |
| Total RAM Bits | — | 1,944,576 |
| Embedded Multipliers | — | 9-bit x 9-bit, in DSP blocks |
| User I/O Count | — | 597 |
| Process Node | — | 0.13 µm all-layer copper SRAM |
| Core Voltage VCCINT | — | 1.5 V typical |
| Configuration | — | JTAG (IEEE 1149.1), Passive Serial, Fast Passive Parallel |
| Maximum Internal Frequency | — | [DATA_NEEDED: internal fMAX per logic cell] |