EP1S25F780C5N vs EP1S25F780I6 Comparaison
Comparaison détaillée côte à côte de EP1S25F780C5N par Intel et EP1S25F780I6 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP1S25F780C5N | EP1S25F780I6 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $595,00 | $162,00 |
| Family | Stratix | Stratix |
| Logic Elements | 25,660 | — |
| Logic Array Blocks (LABs) | 2,566 | — |
| Maximum User I/O | 597 | — |
| Boîtier | 780-ball FBGA, 29 x 29 mm, 1.0 mm pitch | 780-ball FBGA (FineLine BGA, 29 x 29 mm, 1 mm pitch) |
| Process Technology | 130 nm CMOS | — |
| Core Supply Voltage | 1.5 V | — |
| Température de fonctionnement | 0 C to 85 C (Commercial Extended) | 0 °C to +85 °C (Industrial, -I6 grade) |
| Embedded Memory | TriMatrix memory blocks, up to ~1.92 Mbits total | — |
| DSP Blocks | Dedicated multiplier/accumulator blocks | 28 |
| PLLs | 4 | — |
| I/O Banks | 12 | — |
| Maximum Frequency (internal) | up to 500 MHz logic, 420 MHz DSP | — |
| Supported I/O Standards | LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, PCI, PCI-X | — |
| Configuration Modes | Passive Serial, Passive Parallel Sync/Async, JTAG | — |
| Statut RoHS | [DATA_NEEDED: confirm per specific reel lot] | [DATA_NEEDED: RoHS compliance status] |
| Type de montage | Surface Mount (BGA) | Surface Mount (BGA) |
| Niveau MSL | [DATA_NEEDED: MSL rating per JEDEC J-STD-020] | [DATA_NEEDED: MSL rating] |
| Logic Elements (LE) | — | 25,660 |
| Logic Array Blocks (LAB) | — | 2,566 |
| Total RAM Bits | — | 1,944,576 |
| Embedded Multipliers | — | 9-bit x 9-bit, in DSP blocks |
| User I/O Count | — | 597 |
| Process Node | — | 0.13 µm all-layer copper SRAM |
| Core Voltage VCCINT | — | 1.5 V typical |
| Configuration | — | JTAG (IEEE 1149.1), Passive Serial, Fast Passive Parallel |
| Maximum Internal Frequency | — | [DATA_NEEDED: internal fMAX per logic cell] |