EP1S60F1020C7 vs EP1S60F1020C6N Vergleich
Detaillierter Direktvergleich von EP1S60F1020C7 von Altera und EP1S60F1020C6N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP1S60F1020C7 | EP1S60F1020C6N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $1.750,00 | $195,00 |
| Series | Stratix | Stratix |
| Family | Stratix (EP1S60) | Stratix (EP1S) |
| Logic Elements | 57,120 | — |
| Total Memory Bits | 5,215,104 | — |
| Maximum User I/O | 773 | — |
| Gehäuse | 1020-BBGA, FCBGA, 33 x 33 mm, 1.0 mm pitch | — |
| Montageart | Surface Mount | Surface Mount (BGA) |
| Logic Family | CMOS | — |
| Betriebstemperatur | 0C to +85C (Commercial) | 0°C to +85°C (Commercial) |
| Core Supply Voltage | 1.5 V | — |
| Speed Grade | 7 | C6 (mid-tier) |
| Logic Cells / Logic Blocks | 6,570 (per datasheet Section I nomenclature) | — |
| DSP Blocks | Embedded dedicated multiplier / adder blocks | — |
| PLLs | Up to 12 enhanced PLLs per die | — |
| Configuration Method | Serial or parallel with optional decompression | — |
| MSL-Level | 3 (per BGA moisture-sensitivity norms) | [DATA_NEEDED: MSL rating] |
| RoHS-Status | Compliant (lead-free) | Compliant (per 'N' suffix) |
| Logic Elements (LEs) | — | 57,120 |
| Logic Cells | — | 6,570 blocks (per chipdig datasheet summary) |
| Embedded RAM (Total Bits) | — | 5,215,104 bits |
| Embedded Multipliers | — | 773 (18x18) |
| Maximum User I/O Pins | — | Per datasheet, package-dependent (F1020 variant) |
| Package Type | — | 1020-ball FBGA (FineLine BGA), 33 x 33 mm, 1 mm pitch |
| Logic Family / Process | — | CMOS, 0.13 µm |
| Versorgungsspannung | — | Per datasheet (Stratix Device Handbook Vol. 1) |
| Lead-Free / Pb-Free | — | Yes (suffix 'N') |
| Configuration | — | JTAG / Passive Serial / Fast Passive Parallel via MSEL pins |
| PLL Count | — | 12 (per Stratix family datasheet) |
| Memory Block Types | — | TriMatrix (M512, M4K, M-RAM) |