EP1SGX40GF1020I7 vs EP1SGX25FF1020I7 Vergleich

Detaillierter Direktvergleich von EP1SGX40GF1020I7 von Altera und EP1SGX25FF1020I7 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP1SGX40GF1020I7 EP1SGX25FF1020I7
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $1.320,00 $210,00
Family Stratix GX Stratix GX
Series EP1SGX40 EP1SGX25
Logic Cells 41,250 25,660
Configurable Logic Blocks (CLBs) 4,125 2,566
Total RAM Bits 3,423,744 —
User I/O Count 624 —
Number of Terminals 1020 —
Package Type FC-FBGA (1020-ball) —
Package Code BGA —
Terminal Form Ball Ball
Package Shape Square —
Process Technology 130 nm CMOS 130 nm CMOS
Core Voltage 1.5 V —
Combinatorial Delay 9.48 ns per CLB —
Temperature Grade Industrial (I7 suffix) —
Montageart Surface Mount Surface Mount (FC-FBGA)
Core Supply Voltage — 1.5 V
Gehäuse — FC-FBGA-1020 (Flip-Chip Fine-pitch BGA)
Number of Terminals / Balls — 1020
Temperature Grade (suffix 'I') — Industrial
Speed Grade — 7 (highest production grade)
Terminal Pitch — [DATA_NEEDED: terminal pitch]
Combinatorial Delay per CLB — 9.48 ns (per Microchip USA listing)
Combinatorial Delay Variant — [DATA_NEEDED: tPD per CLB variant speed grade]
Maximum Internal Clock Frequency — [DATA_NEEDED: max Fmax in MHz per speed grade]
Embedded Transceivers — Yes (Stratix GX feature)
Configuration Method — SRAM-based (volatile, requires configuration at power-up)
MSL-Level — [DATA_NEEDED: MSL level]
RoHS-Status — [DATA_NEEDED: RoHS compliance]

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