EP1SGX40GF1020I7 vs EP1SGX25FF1020I7 对比

详细并排对比 EP1SGX40GF1020I7 出自 Altera 和 EP1SGX25FF1020I7 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。

Altera

EP1SGX40GF1020I7 - 41,250 Cells Stratix GX FPGA, 130nm, 1020-BGA | Altera

EP1SGX40GF1020I7 Obsolete

Altera

EP1SGX25FF1020I7 Obsolete

参数	EP1SGX40GF1020I7	EP1SGX25FF1020I7
品牌	Altera	Altera
分类	FPGA & CPLD	FPGA & CPLD
生命周期状态	Obsolete	Obsolete
库存状态	有库存	有库存
单价（USD）	$1,320.00	$210.00
Family	Stratix GX	Stratix GX
Series	EP1SGX40	EP1SGX25
Logic Cells	41,250	25,660
Configurable Logic Blocks (CLBs)	4,125	2,566
Total RAM Bits	3,423,744	—
User I/O Count	624	—
Number of Terminals	1020	—
Package Type	FC-FBGA (1020-ball)	—
Package Code	BGA	—
Terminal Form	Ball	Ball
Package Shape	Square	—
Process Technology	130 nm CMOS	130 nm CMOS
Core Voltage	1.5 V	—
Combinatorial Delay	9.48 ns per CLB	—
Temperature Grade	Industrial (I7 suffix)	—
安装类型	Surface Mount	Surface Mount (FC-FBGA)
Core Supply Voltage	—	1.5 V
封装	—	FC-FBGA-1020 (Flip-Chip Fine-pitch BGA)
Number of Terminals / Balls	—	1020
Temperature Grade (suffix 'I')	—	Industrial
Speed Grade	—	7 (highest production grade)
Terminal Pitch	—	[DATA_NEEDED: terminal pitch]
Combinatorial Delay per CLB	—	9.48 ns (per Microchip USA listing)
Combinatorial Delay Variant	—	[DATA_NEEDED: tPD per CLB variant speed grade]
Maximum Internal Clock Frequency	—	[DATA_NEEDED: max Fmax in MHz per speed grade]
Embedded Transceivers	—	Yes (Stratix GX feature)
Configuration Method	—	SRAM-based (volatile, requires configuration at power-up)
MSL 等级	—	[DATA_NEEDED: MSL level]
RoHS 状态	—	[DATA_NEEDED: RoHS compliance]