EP1SGX40GF800I7 vs EP1SGX40GF800C5N Vergleich
Detaillierter Direktvergleich von EP1SGX40GF800I7 von Altera und EP1SGX40GF800C5N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP1SGX40GF800I7 | EP1SGX40GF800C5N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $1.325,00 | $198,75 |
| Family | Stratix GX | Stratix GX |
| Series | Stratix GX FPGA | — |
| Logic Elements (LE) | 41,250 | — |
| Embedded Memory | 3,423,744 bits | — |
| Embedded Multipliers (18x18) | 624 | — |
| High-Speed Transceivers (SERDES) | 20 channels, up to 3.125 Gbps | — |
| Gehäuse | 800-ball FineLine BGA (GF) | 780-pin FineLine BGA |
| Betriebstemperatur | -40C to +100C (industrial, I grade) | Commercial (0C to +85C) |
| Speed Grade | -7 | -5 (slower than -6/-7) |
| PLL Count | 12 (logic + transceiver) | — |
| User I/O Banks | [DATA_NEEDED: number of user I/O banks and pins] | — |
| Maximum User I/O | [DATA_NEEDED: max user I/O count] | — |
| Supply Voltage Core | [DATA_NEEDED: VCCINT nominal] | — |
| Configuration Method | Enhanced configuration device / Passive serial / JTAG | EPC enhanced configuration devices or JTAG |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: explicit RoHS statement for this specific MPN] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead-free finish] |
| MSL-Level | [DATA_NEEDED: moisture sensitivity level] | — |
| Transceiver Protocols Supported | PCI Express, Gigabit Ethernet, XAUI, Serial RapidIO, Fibre Channel | — |
| Logic Elements | — | 41,250 |
| Total RAM Bits | — | 3,432,192 (3.4 Mbit) |
| DSP Blocks | — | 14 |
| Embedded Multipliers (9-bit equivalent) | — | 56 |
| Transceiver Channels | — | 20 (up to 3.1875 Gbps per channel) |
| Maximum User I/O Pins | — | [DATA_NEEDED: max user I/O count for 780-pin BGA] |
| PLLs | — | 24 |
| Clock Networks | — | 8 phase-locked |
| Core Voltage | — | 1.5 V |
| Process Technology | — | 0.13 µm SRAM |