EP20K100CF144C7ES vs EP20K100CF144C7 Vergleich
Detaillierter Direktvergleich von EP20K100CF144C7ES von Intel und EP20K100CF144C7 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP20K100CF144C7ES | EP20K100CF144C7 |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $171,00 | $28,40 |
| Family | APEX-20K | APEX-20K Field Programmable Gate Array |
| Typical Gates | 100,000 | — |
| Logic Elements | 4,160 | — |
| Embedded Memory (RAM bits) | 53,248 | — |
| User I/O Pins | 93 | — |
| DLLs / Clock Management | 4 DLLs | — |
| Gehäuse | 144-LQFP (20x20 mm) | — |
| Montageart | Surface Mount | Surface Mount |
| Speed Grade | C7 (commercial, mid-speed) | C7 (commercial) |
| Betriebstemperatur | 0C to +85C (commercial) | 0C to +85C (commercial) |
| Core Voltage | 1.8 V (typical APEX-20K VCCINT) | — |
| I/O Voltage Reference | MultiVolt I/O - 3.3 V / 5 V tolerant | — |
| Architecture | MultiCore (LUT + Embedded System Blocks) | — |
| Programming File Format | Quartus II / MAX+PLUS II SOF / POF | — |
| Variant Suffix | ES (engineering sample / special order) | — |
| MSL-Level | [DATA_NEEDED: MSL Level] | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Series | — | APEX-20K |
| Logic Elements / Cells | — | 4,160 |
| Total RAM Bits | — | 53,248 |
| Number of Logic Elements | — | 4,160 |
| Number of I/O | — | 93 |
| Number of Gates | — | 100,000 system gates |
| Voltage - Supply | — | 1.8 V core, 3.3 V I/O (typical APEX-20K rails) |
| Gehäuse / Bauform | — | 144-LQFP |
| Package Dimensions | — | 22 x 22 mm, 0.5 mm pitch |
| Process Technology | — | 0.18 micron CMOS SRAM |
| Configuration Mode | — | Passive Serial, JTAG (IEEE 1149.1) |
| PLLs | — | 4 (per APEX-20K family architecture) |